Struct stm32_metapac::rcc::regs::Bdcr

#[repr(transparent)]
pub struct Bdcr(pub u32);

Expand description

RCC Backup domain control register

Tuple Fields§

§0: u32

Implementations§

§

impl Bdcr

pub const fn lseon(&self) -> bool

LSE oscillator enable Set and cleared by software.

pub fn set_lseon(&mut self, val: bool)

LSE oscillator enable Set and cleared by software.

pub const fn lserdy(&self) -> bool

LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

pub fn set_lserdy(&mut self, val: bool)

LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

pub const fn lsebyp(&self) -> bool

LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).

pub fn set_lsebyp(&mut self, val: bool)

LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).

pub const fn lsedrv(&self) -> Lsedrv

LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in ’Xtal mode when it is not in bypass mode.

pub fn set_lsedrv(&mut self, val: Lsedrv)

LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in ’Xtal mode when it is not in bypass mode.

pub const fn lsecsson(&self) -> bool

CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit.

pub fn set_lsecsson(&mut self, val: bool)

CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit.

pub const fn lsecssd(&self) -> bool

CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE).

pub fn set_lsecssd(&mut self, val: bool)

CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE).

pub const fn lsesysen(&self) -> bool

LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE.

pub fn set_lsesysen(&mut self, val: bool)

LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE.

pub const fn rtcsel(&self) -> Rtcsel

RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.

pub fn set_rtcsel(&mut self, val: Rtcsel)

RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.

pub const fn lsesysrdy(&self) -> bool

LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

pub fn set_lsesysrdy(&mut self, val: bool)

LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

pub const fn lsegfon(&self) -> bool

LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)

pub fn set_lsegfon(&mut self, val: bool)

LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)

pub const fn rtcen(&self) -> bool

RTC and TAMP clock enable Set and cleared by software.

pub fn set_rtcen(&mut self, val: bool)

RTC and TAMP clock enable Set and cleared by software.

pub const fn bdrst(&self) -> bool

Backup domain software reset Set and cleared by software.

pub fn set_bdrst(&mut self, val: bool)

Backup domain software reset Set and cleared by software.

pub const fn lscoen(&self) -> bool

Low-speed clock output (LSCO) enable Set and cleared by software.

pub fn set_lscoen(&mut self, val: bool)

Low-speed clock output (LSCO) enable Set and cleared by software.

pub const fn lscosel(&self) -> Lscosel

Low-speed clock output selection Set and cleared by software.

pub fn set_lscosel(&mut self, val: Lscosel)

Low-speed clock output selection Set and cleared by software.

pub const fn lsion(&self) -> bool

LSI oscillator enable Set and cleared by software.

pub fn set_lsion(&mut self, val: bool)

LSI oscillator enable Set and cleared by software.

pub const fn lsirdy(&self) -> bool

LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.

pub fn set_lsirdy(&mut self, val: bool)

LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.

pub const fn lsiprediv(&self) -> Lsiprediv

Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 Î¼s after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.

pub fn set_lsiprediv(&mut self, val: Lsiprediv)

Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 Î¼s after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.