Struct stm32_metapac::flash::regs::Seccr

#[repr(transparent)]
pub struct Seccr(pub u32);

Expand description

FLASH secure control register

Tuple Fields§

§0: u32

Implementations§

§

impl Seccr

pub const fn pg(&self) -> SeccrPg

Secure programming

pub fn set_pg(&mut self, val: SeccrPg)

Secure programming

pub const fn per(&self) -> SeccrPer

Secure page erase

pub fn set_per(&mut self, val: SeccrPer)

Secure page erase

pub const fn mer1(&self) -> bool

Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set.

pub fn set_mer1(&mut self, val: bool)

Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set.

pub const fn pnb(&self) -> u8

Secure page number selection These bits select the page to erase: …

pub fn set_pnb(&mut self, val: u8)

Secure page number selection These bits select the page to erase: …

pub const fn bker(&self) -> SeccrBker

Secure bank selection for page erase

pub fn set_bker(&mut self, val: SeccrBker)

Secure bank selection for page erase

pub const fn bwr(&self) -> bool

Secure burst write programming mode When set, this bit selects the burst write programming mode.

pub fn set_bwr(&mut self, val: bool)

Secure burst write programming mode When set, this bit selects the burst write programming mode.

pub const fn mer2(&self) -> bool

Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set.

pub fn set_mer2(&mut self, val: bool)

Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set.

pub const fn strt(&self) -> bool

Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR.

pub fn set_strt(&mut self, val: bool)

Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR.

pub const fn eopie(&self) -> SeccrEopie

Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1.

pub fn set_eopie(&mut self, val: SeccrEopie)

Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1.

pub const fn errie(&self) -> SeccrErrie

Secure error interrupt enable

pub fn set_errie(&mut self, val: SeccrErrie)

Secure error interrupt enable

pub const fn rderrie(&self) -> bool

Secure PCROP read error interrupt enable

pub fn set_rderrie(&mut self, val: bool)

Secure PCROP read error interrupt enable

pub const fn inv(&self) -> bool

Flash memory security state invert This bit inverts the Flash memory security state.

pub fn set_inv(&mut self, val: bool)

Flash memory security state invert This bit inverts the Flash memory security state.

pub const fn lock(&self) -> bool

Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.

pub fn set_lock(&mut self, val: bool)

Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.