Struct stm32_metapac::rcc::regs::Ahb2smenr2

#[repr(transparent)]
pub struct Ahb2smenr2(pub u32);

RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2

Tuple Fields

0: u32

Implementations

impl Ahb2smenr2

pub const fn fsmcsmen(&self) -> bool

FSMC clocks enable during Sleep and Stop modes Set and cleared by software.

pub fn set_fsmcsmen(&mut self, val: bool)

FSMC clocks enable during Sleep and Stop modes Set and cleared by software.

pub const fn octospi1smen(&self) -> bool

OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software.

pub fn set_octospi1smen(&mut self, val: bool)

OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software.

pub const fn octospi2smen(&self) -> bool

OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software.

pub fn set_octospi2smen(&mut self, val: bool)

OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software.

pub const fn hspi1smen(&self) -> bool

HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_hspi1smen(&mut self, val: bool)

HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn sram6smen(&self) -> bool

SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_sram6smen(&mut self, val: bool)

SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn sram5smen(&self) -> bool

SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_sram5smen(&mut self, val: bool)

SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

Trait Implementations

impl Clone for Ahb2smenr2

fn clone(&self) -> Ahb2smenr2

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Ahb2smenr2

fn default() -> Ahb2smenr2

Returns the “default value” for a type.

impl PartialEq for Ahb2smenr2

fn eq(&self, other: &Ahb2smenr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ahb2smenr2

impl Eq for Ahb2smenr2

impl StructuralPartialEq for Ahb2smenr2