Struct stm32_metapac::dsihost::regs::Clcr

#[repr(transparent)]
pub struct Clcr(pub u32);

DSI Host clock lane configuration register.

Tuple Fields

0: u32

Implementations

impl Clcr

pub const fn dpcc(&self) -> bool

D-PHY clock control This bit controls the D-PHY clock state:.

pub fn set_dpcc(&mut self, val: bool)

D-PHY clock control This bit controls the D-PHY clock state:.

pub const fn acr(&self) -> bool

Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.

pub fn set_acr(&mut self, val: bool)

Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.

Trait Implementations

impl Clone for Clcr

fn clone(&self) -> Clcr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Clcr

fn default() -> Clcr

Returns the “default value” for a type.

impl PartialEq for Clcr

fn eq(&self, other: &Clcr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Clcr

impl Eq for Clcr

impl StructuralPartialEq for Clcr