Struct stm32_metapac::rcc::regs::Ahb2enr2

#[repr(transparent)]
pub struct Ahb2enr2(pub u32);

RCC AHB2 peripheral clock enable register 2

Tuple Fields

0: u32

Implementations

impl Ahb2enr2

pub const fn fsmcen(&self) -> bool

FSMC clock enable Set and cleared by software.

pub fn set_fsmcen(&mut self, val: bool)

FSMC clock enable Set and cleared by software.

pub const fn octospi1en(&self) -> bool

OCTOSPI1 clock enable Set and cleared by software.

pub fn set_octospi1en(&mut self, val: bool)

OCTOSPI1 clock enable Set and cleared by software.

pub const fn octospi2en(&self) -> bool

OCTOSPI2 clock enable Set and cleared by software.

pub fn set_octospi2en(&mut self, val: bool)

OCTOSPI2 clock enable Set and cleared by software.

pub const fn hspi1en(&self) -> bool

HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_hspi1en(&mut self, val: bool)

HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn sram6en(&self) -> bool

SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_sram6en(&mut self, val: bool)

SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn sram5en(&self) -> bool

SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_sram5en(&mut self, val: bool)

SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

Trait Implementations

impl Clone for Ahb2enr2

fn clone(&self) -> Ahb2enr2

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Ahb2enr2

fn default() -> Ahb2enr2

Returns the “default value” for a type.

impl PartialEq for Ahb2enr2

fn eq(&self, other: &Ahb2enr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ahb2enr2

impl Eq for Ahb2enr2

impl StructuralPartialEq for Ahb2enr2