Struct stm32_metapac::rcc::regs::Apb1enr1

#[repr(transparent)]
pub struct Apb1enr1(pub u32);

Expand description

RCC APB1 peripheral clock enable register 1

Tuple Fields§

§0: u32

Implementations§

§

impl Apb1enr1

pub const fn tim2en(&self) -> bool

TIM2 clock enable Set and cleared by software.

pub fn set_tim2en(&mut self, val: bool)

TIM2 clock enable Set and cleared by software.

pub const fn tim3en(&self) -> bool

TIM3 clock enable Set and cleared by software.

pub fn set_tim3en(&mut self, val: bool)

TIM3 clock enable Set and cleared by software.

pub const fn tim4en(&self) -> bool

TIM4 clock enable Set and cleared by software.

pub fn set_tim4en(&mut self, val: bool)

TIM4 clock enable Set and cleared by software.

pub const fn tim5en(&self) -> bool

TIM5 clock enable Set and cleared by software.

pub fn set_tim5en(&mut self, val: bool)

TIM5 clock enable Set and cleared by software.

pub const fn tim6en(&self) -> bool

TIM6 clock enable Set and cleared by software.

pub fn set_tim6en(&mut self, val: bool)

TIM6 clock enable Set and cleared by software.

pub const fn tim7en(&self) -> bool

TIM7 clock enable Set and cleared by software.

pub fn set_tim7en(&mut self, val: bool)

TIM7 clock enable Set and cleared by software.

pub const fn wwdgen(&self) -> bool

WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset.

pub fn set_wwdgen(&mut self, val: bool)

WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset.

pub const fn spi2en(&self) -> bool

SPI2 clock enable Set and cleared by software.

pub fn set_spi2en(&mut self, val: bool)

SPI2 clock enable Set and cleared by software.

pub const fn usart2en(&self) -> bool

USART2 clock enable Set and cleared by software.

pub fn set_usart2en(&mut self, val: bool)

USART2 clock enable Set and cleared by software.

pub const fn usart3en(&self) -> bool

USART3 clock enable Set and cleared by software.

pub fn set_usart3en(&mut self, val: bool)

USART3 clock enable Set and cleared by software.

pub const fn uart4en(&self) -> bool

UART4 clock enable Set and cleared by software.

pub fn set_uart4en(&mut self, val: bool)

UART4 clock enable Set and cleared by software.

pub const fn uart5en(&self) -> bool

UART5 clock enable Set and cleared by software.

pub fn set_uart5en(&mut self, val: bool)

UART5 clock enable Set and cleared by software.

pub const fn i2c1en(&self) -> bool

I2C1 clock enable Set and cleared by software.

pub fn set_i2c1en(&mut self, val: bool)

I2C1 clock enable Set and cleared by software.

pub const fn i2c2en(&self) -> bool

I2C2 clock enable Set and cleared by software.

pub fn set_i2c2en(&mut self, val: bool)

I2C2 clock enable Set and cleared by software.

pub const fn crsen(&self) -> bool

CRS clock enable Set and cleared by software.

pub fn set_crsen(&mut self, val: bool)

CRS clock enable Set and cleared by software.

pub const fn usart6en(&self) -> bool

USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_usart6en(&mut self, val: bool)

USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.