Struct stm32_metapac::dsihost::regs::Cltcr
#[repr(transparent)]pub struct Cltcr(pub u32);
Expand description
DSI Host clock lane timer configuration register.
Tuple Fields§
§0: u32
Implementations§
§impl Cltcr
impl Cltcr
pub const fn lp2hs_time(&self) -> u16
pub const fn lp2hs_time(&self) -> u16
Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâpower to high-speed transmission measured in lane byte clock cycles.
pub fn set_lp2hs_time(&mut self, val: u16)
pub fn set_lp2hs_time(&mut self, val: u16)
Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâpower to high-speed transmission measured in lane byte clock cycles.
pub const fn hs2lp_time(&self) -> u16
pub const fn hs2lp_time(&self) -> u16
High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâspeed to low-power transmission measured in lane byte clock cycles.
pub fn set_hs2lp_time(&mut self, val: u16)
pub fn set_hs2lp_time(&mut self, val: u16)
High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâspeed to low-power transmission measured in lane byte clock cycles.