Struct stm32_metapac::hspi::regs::Wtcr

#[repr(transparent)]
pub struct Wtcr(pub u32);

HSPI write timing configuration register.

Tuple Fields

0: u32

Implementations

impl Wtcr

pub const fn dcyc(&self) -> u8

Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.

pub fn set_dcyc(&mut self, val: u8)

Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.

Trait Implementations

impl Clone for Wtcr

fn clone(&self) -> Wtcr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Wtcr

fn default() -> Wtcr

Returns the “default value” for a type.

impl PartialEq for Wtcr

fn eq(&self, other: &Wtcr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Wtcr

impl Eq for Wtcr

impl StructuralPartialEq for Wtcr