Struct stm32_metapac::rcc::regs::Ahb1enr

#[repr(transparent)]
pub struct Ahb1enr(pub u32);

Expand description

RCC AHB1 peripheral clock enable register

Tuple Fields§

§0: u32

Implementations§

§

impl Ahb1enr

pub const fn gpdma1en(&self) -> bool

GPDMA1 clock enable Set and cleared by software.

pub fn set_gpdma1en(&mut self, val: bool)

GPDMA1 clock enable Set and cleared by software.

pub const fn cordicen(&self) -> bool

CORDIC clock enable Set and cleared by software.

pub fn set_cordicen(&mut self, val: bool)

CORDIC clock enable Set and cleared by software.

pub const fn fmacen(&self) -> bool

FMAC clock enable Set and reset by software.

pub fn set_fmacen(&mut self, val: bool)

FMAC clock enable Set and reset by software.

pub const fn mdf1en(&self) -> bool

MDF1 clock enable Set and reset by software.

pub fn set_mdf1en(&mut self, val: bool)

MDF1 clock enable Set and reset by software.

pub const fn flashen(&self) -> bool

FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.

pub fn set_flashen(&mut self, val: bool)

FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.

pub const fn crcen(&self) -> bool

CRC clock enable Set and cleared by software.

pub fn set_crcen(&mut self, val: bool)

CRC clock enable Set and cleared by software.

pub const fn jpegen(&self) -> bool

JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_jpegen(&mut self, val: bool)

JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn tscen(&self) -> bool

Touch sensing controller clock enable Set and cleared by software.

pub fn set_tscen(&mut self, val: bool)

Touch sensing controller clock enable Set and cleared by software.

pub const fn ramcfgen(&self) -> bool

RAMCFG clock enable Set and cleared by software.

pub fn set_ramcfgen(&mut self, val: bool)

RAMCFG clock enable Set and cleared by software.

pub const fn dma2den(&self) -> bool

DMA2D clock enable Set and cleared by software.

pub fn set_dma2den(&mut self, val: bool)

DMA2D clock enable Set and cleared by software.

pub const fn gfxmmuen(&self) -> bool

GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_gfxmmuen(&mut self, val: bool)

GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn gpu2den(&self) -> bool

GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_gpu2den(&mut self, val: bool)

GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn dcache2en(&self) -> bool

DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub fn set_dcache2en(&mut self, val: bool)

DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

pub const fn gtzc1en(&self) -> bool

GTZC1 clock enable Set and reset by software.

pub fn set_gtzc1en(&mut self, val: bool)

GTZC1 clock enable Set and reset by software.

pub const fn bkpsramen(&self) -> bool

BKPSRAM clock enable Set and reset by software.

pub fn set_bkpsramen(&mut self, val: bool)

BKPSRAM clock enable Set and reset by software.

pub const fn dcache1en(&self) -> bool

DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed.

pub fn set_dcache1en(&mut self, val: bool)

DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed.