Struct stm32_metapac::rcc::regs::Cfgr2
#[repr(transparent)]pub struct Cfgr2(pub u32);
Expand description
RCC clock configuration register 2
Tuple Fields§
§0: u32
Implementations§
§impl Cfgr2
impl Cfgr2
pub const fn hpre(&self) -> Hpre
pub const fn hpre(&self) -> Hpre
AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided
pub fn set_hpre(&mut self, val: Hpre)
pub fn set_hpre(&mut self, val: Hpre)
AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided
pub const fn ppre1(&self) -> Ppre
pub const fn ppre1(&self) -> Ppre
APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided
pub fn set_ppre1(&mut self, val: Ppre)
pub fn set_ppre1(&mut self, val: Ppre)
APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided