Struct stm32_metapac::dbgmcu::regs::Apb1lfzr
#[repr(transparent)]pub struct Apb1lfzr(pub u32);
Expand description
APB1L peripheral freeze register
Tuple Fields§
§0: u32
Implementations§
§impl Apb1lfzr
impl Apb1lfzr
pub const fn dbg_tim2_stop(&self) -> bool
pub const fn dbg_tim2_stop(&self) -> bool
TIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM2SEC.
pub fn set_dbg_tim2_stop(&mut self, val: bool)
pub fn set_dbg_tim2_stop(&mut self, val: bool)
TIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM2SEC.
pub const fn dbg_tim3_stop(&self) -> bool
pub const fn dbg_tim3_stop(&self) -> bool
TIM3 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM3SEC.
pub fn set_dbg_tim3_stop(&mut self, val: bool)
pub fn set_dbg_tim3_stop(&mut self, val: bool)
TIM3 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM3SEC.
pub const fn dbg_wwdg_stop(&self) -> bool
pub const fn dbg_wwdg_stop(&self) -> bool
WWDG stop in CPU debug Write access can be protected by GTZC_TZSC.WWDGSEC
pub fn set_dbg_wwdg_stop(&mut self, val: bool)
pub fn set_dbg_wwdg_stop(&mut self, val: bool)
WWDG stop in CPU debug Write access can be protected by GTZC_TZSC.WWDGSEC
pub const fn dbg_iwdg_stop(&self) -> bool
pub const fn dbg_iwdg_stop(&self) -> bool
IWDG stop in CPU debug Write access can be protected by GTZC_TZSC.IWDGSEC.
pub fn set_dbg_iwdg_stop(&mut self, val: bool)
pub fn set_dbg_iwdg_stop(&mut self, val: bool)
IWDG stop in CPU debug Write access can be protected by GTZC_TZSC.IWDGSEC.
pub const fn dbg_i2c1_stop(&self) -> bool
pub const fn dbg_i2c1_stop(&self) -> bool
I2C1 SMBUS timeout stop in CPU debug Write access can be protected by GTZC_TZSC.I2C1SEC.
pub fn set_dbg_i2c1_stop(&mut self, val: bool)
pub fn set_dbg_i2c1_stop(&mut self, val: bool)
I2C1 SMBUS timeout stop in CPU debug Write access can be protected by GTZC_TZSC.I2C1SEC.