Struct stm32_metapac::dbgmcu::regs::Cr
#[repr(transparent)]pub struct Cr(pub u32);
Expand description
status and configuration register
Tuple Fields§
§0: u32
Implementations§
§impl Cr
impl Cr
pub const fn dbg_stop(&self) -> bool
pub const fn dbg_stop(&self) -> bool
Allows debug in Stop mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state.
pub fn set_dbg_stop(&mut self, val: bool)
pub fn set_dbg_stop(&mut self, val: bool)
Allows debug in Stop mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state.
pub const fn dbg_standby(&self) -> bool
pub const fn dbg_standby(&self) -> bool
Allows debug in Standby mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed.
pub fn set_dbg_standby(&mut self, val: bool)
pub fn set_dbg_standby(&mut self, val: bool)
Allows debug in Standby mode Write access can be protected by PWR_SECCFGR.LPMSEC. The CPU debug and clocks remain active and the HSI oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed.