Struct stm32_metapac::rcc::regs::Apb1smenr1
#[repr(transparent)]pub struct Apb1smenr1(pub u32);
Expand description
RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1
Tuple Fields§
§0: u32
Implementations§
§impl Apb1smenr1
impl Apb1smenr1
pub const fn tim2smen(&self) -> bool
pub const fn tim2smen(&self) -> bool
TIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_tim2smen(&mut self, val: bool)
pub fn set_tim2smen(&mut self, val: bool)
TIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn tim3smen(&self) -> bool
pub const fn tim3smen(&self) -> bool
TIM3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_tim3smen(&mut self, val: bool)
pub fn set_tim3smen(&mut self, val: bool)
TIM3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn wwdgsmen(&self) -> bool
pub const fn wwdgsmen(&self) -> bool
Window watchdog bus clock enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_wwdgsmen(&mut self, val: bool)
pub fn set_wwdgsmen(&mut self, val: bool)
Window watchdog bus clock enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn usart2smen(&self) -> bool
pub const fn usart2smen(&self) -> bool
USART2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
pub fn set_usart2smen(&mut self, val: bool)
pub fn set_usart2smen(&mut self, val: bool)
USART2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
pub const fn i2c1smen(&self) -> bool
pub const fn i2c1smen(&self) -> bool
I2C1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
pub fn set_i2c1smen(&mut self, val: bool)
pub fn set_i2c1smen(&mut self, val: bool)
I2C1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
Trait Implementations§
§impl Clone for Apb1smenr1
impl Clone for Apb1smenr1
§fn clone(&self) -> Apb1smenr1
fn clone(&self) -> Apb1smenr1
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read more§impl Default for Apb1smenr1
impl Default for Apb1smenr1
§fn default() -> Apb1smenr1
fn default() -> Apb1smenr1
§impl PartialEq for Apb1smenr1
impl PartialEq for Apb1smenr1
§fn eq(&self, other: &Apb1smenr1) -> bool
fn eq(&self, other: &Apb1smenr1) -> bool
self
and other
values to be equal, and is used
by ==
.