Struct stm32_metapac::rcc::regs::Cfgr1

#[repr(transparent)]
pub struct Cfgr1(pub u32);

Expand description

RCC clock configuration register 1

Tuple Fields§

§0: u32

Implementations§

§

impl Cfgr1

pub const fn sw(&self) -> Sw

system clock switch Set and cleared by software to select system clock source (SYSCLK). Cleared by hardware when entering Stop and Standby modes When selecting HSE directly or indirectly as system clock and HSE oscillator clock security fails, cleared by hardware.

pub fn set_sw(&mut self, val: Sw)

system clock switch Set and cleared by software to select system clock source (SYSCLK). Cleared by hardware when entering Stop and Standby modes When selecting HSE directly or indirectly as system clock and HSE oscillator clock security fails, cleared by hardware.

pub const fn sws(&self) -> Sw

system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock.

pub fn set_sws(&mut self, val: Sw)

system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock.

pub const fn mcosel(&self) -> Mcosel

microcontroller clock output Set and cleared by software. others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

pub fn set_mcosel(&mut self, val: Mcosel)

microcontroller clock output Set and cleared by software. others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

pub const fn mcopre(&self) -> Mcopre

microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. others: not allowed

pub fn set_mcopre(&mut self, val: Mcopre)

microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. others: not allowed