Struct stm32_metapac::flash::regs::Eccr

#[repr(transparent)]
pub struct Eccr(pub u32);

Expand description

ECC register

Tuple Fields§

§0: u32

Implementations§

§

impl Eccr

pub const fn addr_ecc(&self) -> u32

ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices.

pub fn set_addr_ecc(&mut self, val: u32)

ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices.

pub const fn sysf_ecc(&self) -> bool

System memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system memory.

pub fn set_sysf_ecc(&mut self, val: bool)

System memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system memory.

pub const fn eccie(&self) -> bool

ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the ECCR register is set.

pub fn set_eccie(&mut self, val: bool)

ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the ECCR register is set.

pub const fn eccc(&self) -> bool

ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1.

pub fn set_eccc(&mut self, val: bool)

ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1.

pub const fn eccd(&self) -> bool

ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1.

pub fn set_eccd(&mut self, val: bool)

ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1.