Struct stm32_metapac::rcc::regs::Pll1divr

#[repr(transparent)]
pub struct Pll1divr(pub u32);

RCC PLL1 dividers register

Tuple Fields

0: u32

Implementations

impl Pll1divr

pub const fn plln(&self) -> u16

Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … … others: reserved VCO output frequency = F_{ref1_ck} x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: Multiplication factor for PLL1 VCO between 4 and 512 input frequency F_{ref1_ck} between 4 and 16�MHz

pub fn set_plln(&mut self, val: u16)

Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … … others: reserved VCO output frequency = F_{ref1_ck} x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: Multiplication factor for PLL1 VCO between 4 and 512 input frequency F_{ref1_ck} between 4 and 16�MHz

pub const fn pllp(&self) -> u8

PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1pclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. …

pub fn set_pllp(&mut self, val: u8)

PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1pclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. …

pub const fn pllq(&self) -> u8

PLL1 DIVQ division factor Set and reset by software to control the frequency of the PLl1QCLK clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …

pub fn set_pllq(&mut self, val: u8)

PLL1 DIVQ division factor Set and reset by software to control the frequency of the PLl1QCLK clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …

pub const fn pllr(&self) -> u8

PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1rclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …

pub fn set_pllr(&mut self, val: u8)

PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1rclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …

Trait Implementations

impl Clone for Pll1divr

fn clone(&self) -> Pll1divr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Pll1divr

fn default() -> Pll1divr

Returns the “default value” for a type.

impl PartialEq for Pll1divr

fn eq(&self, other: &Pll1divr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Pll1divr

impl Eq for Pll1divr

impl StructuralPartialEq for Pll1divr