Module csi 

CSI-2 Host controller.

Receives MIPI CSI-2 packets from an external image sensor and forwards the stream to the DCMIPP pixel pipeline. This driver covers the host / lane merger / D-PHY power control and timing: enable/disable, lane selection, D-PHY frequency configuration, per-virtual-channel start/stop, and error reporting. Pixel-format and memory-destination configuration lives on the DCMIPP side (see the dcmipp module).

CSI-2 data and clock lanes are fixed differential MIPI D-PHY pads on the chip and are not GPIO-muxable, so this driver has no pin traits or new_with_pins constructor.

Virtual channels

Up to four virtual channels (VC0..VC3) can be enabled simultaneously via the Config::virtual_channels bitmask. Each enabled VC latches all data types (ALLDT = 1) by default; callers that need finer filtering can program VCxCFGR1..4 directly through pac::CSI.

D-PHY init

The RM0486 §40.6 init sequence is applied in Csi::new:

1. PRCR.PEN = 1 (release the D-PHY digital section from reset).
2. PFCR.DLD = 0 (force Rx mode on data lane 0); PFCR.CCFR = round((F_cfg MHz − 17) × 4); PFCR.HSFR = high-speed frequency band from data_rate_mbps.
3. PTCR0.TRSEN = 0, PTCR0.TCKEN = 0 (disable the D-PHY test interface).
4. LMCFGR lane count + D0/D1 mapping.
5. VCxCFGR1.ALLDT = 1 for every enabled VC.
6. PCR lane enables.

HSFR is derived from data_rate_mbps using the linear approximation ((rate − 80) / 40).clamp(0, 0x7F). This is the same form used by the published ST D-PHY drivers and is a reasonable band estimate for most rates between 80 Mbps and 2.5 Gbps; callers that need a specific band (e.g. to match an exact PLL output) can pin it with Config::hs_freq_range_override.

Structs

Config

CSI-2 Host configuration.

Csi

CSI-2 Host driver.

InterruptHandler

Interrupt handler.

Enums

Error

CSI-2 Host error.

LaneCount

Number of CSI-2 data lanes in use.

Traits

Instance

CSI-2 Host instance.