Structsยง
- Cpu0
Lock Reg - Miscalleneous control signals for in Cortex M33 (CPU0)
- Master
SecAnti PolReg - master secure level anti-pole register
- Master
SecLevel - master secure level register
- Misc
Ctrl DpReg - secure control duplicate register
- Misc
Ctrl Reg - secure control register
- SecCtrl
AhbPort7 Slave0 Rule - Security access rules for AHB peripherals.
- SecCtrl
AhbPort7 Slave1 Rule - Security access rules for AHB peripherals.
- SecCtrl
AhbPort8 Slave0 Rule - Security access rules for AHB peripherals.
- SecCtrl
AhbPort8 Slave1 Rule - Security access rules for AHB peripherals.
- SecCtrl
AhbPort9 Slave0 Rule - Security access rules for AHB peripherals.
- SecCtrl
AhbPort9 Slave1 Rule - Security access rules for AHB peripherals.
- SecCtrl
AhbSec Ctrl MemRule - Security access rules for AHB_SEC_CTRL_AHB.
- SecCtrl
ApbBridge0 MemCtrl0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
- SecCtrl
ApbBridge0 MemCtrl1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
- SecCtrl
ApbBridge0 MemCtrl2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
- SecCtrl
ApbBridge1 MemCtrl0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
- SecCtrl
ApbBridge1 MemCtrl1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
- SecCtrl
ApbBridge1 MemCtrl2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
- SecCtrl
ApbBridge1 MemCtrl3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
- SecCtrl
ApbBridge Slave Rule - Security access rules for both APB Bridges slaves.
- SecCtrl
Flash MemRule0 - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total.
- SecCtrl
Flash RomSlave Rule - Security access rules for Flash and ROM slaves.
- SecCtrl
Ram0 MemRule0 - Security access rules for RAM0 slaves.
- SecCtrl
Ram0 Slave Rule - Security access rules for RAM0 slaves.
- SecCtrl
Ram1 MemRule0 - Security access rules for RAM1 slaves.
- SecCtrl
Ram1 Slave Rule - Security access rules for RAM1 slaves.
- SecCtrl
Ram2 MemRule0 - Security access rules for RAM2 slaves.
- SecCtrl
Ram2 Slave Rule - Security access rules for RAM2 slaves.
- SecCtrl
Ramx MemRule0 - Security access rules for RAMX slaves.
- SecCtrl
Ramx Slave Rule - Security access rules for RAMX slaves.
- SecCtrl
RomMem Rule0 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
- SecCtrl
RomMem Rule1 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
- SecCtrl
RomMem Rule2 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
- SecCtrl
RomMem Rule3 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
- SecCtrl
UsbHs MemRule - Security access rules for RAM_USB_HS.
- SecCtrl
UsbHs Slave Rule - Security access rules for USB High speed RAM slaves.
- SecGpio
Mask0 - Secure GPIO mask for port 0 pins.
- SecGpio
Mask1 - Secure GPIO mask for port 1 pins.
- SecMask
Lock - Security General Purpose register access control.
- SecVio
Addr - most recent security violation address for AHB layer n
- SecVio
Info Valid - security violation address/information registers valid flags
- SecVio
Misc Info - most recent security violation miscellaneous information for AHB layer n