Module regs
Source - Cccr
- CC Control Register
- Dbtp
- Data Bit Timing Prescaler Register
- Ecr
- Error Counter Register
- Etscc
- External Timestamp Counter Configuration
- Etscv
- External Timestamp Counter Value
- Gfc
- Global Filter Configuration
- Hpms
- High Priority Message Status
- Ie
- Interrupt Enable
- Ile
- Interrupt Line Enable
- Ils
- Interrupt Line Select
- Ir
- Interrupt Register
- Mrba
- CAN Message RAM Base Address
- Nbtp
- Nominal Bit Timing and Prescaler Register
- Ndat1
- New Data 1
- Ndat2
- New Data 2
- Psr
- Protocol Status Register
- Rxbc
- Rx Buffer Configuration
- Rxesc
- Rx Buffer and FIFO Element Size Configuration
- Rxf0a
- Rx FIFO 0 Acknowledge
- Rxf0c
- Rx FIFO 0 Configuration
- Rxf0s
- Rx FIFO 0 Status
- Rxf1a
- Rx FIFO 1 Acknowledge
- Rxf1c
- Rx FIFO 1 Configuration
- Rxf1s
- Rx FIFO 1 Status
- Sidfc
- Standard ID Filter Configuration
- Tdcr
- Transmitter Delay Compensator Register
- Test
- Test Register
- Tocc
- Timeout Counter Configuration
- Tocv
- Timeout Counter Value
- Tscc
- Timestamp Counter Configuration
- Tscv
- Timestamp Counter Value
- Txbar
- Tx Buffer Add Request
- Txbc
- Tx Buffer Configuration
- Txbcf
- Tx Buffer Cancellation Finished
- Txbcie
- Tx Buffer Cancellation Finished Interrupt Enable
- Txbcr
- Tx Buffer Cancellation Request
- Txbrp
- Tx Buffer Request Pending
- Txbtie
- Tx Buffer Transmission Interrupt Enable
- Txbto
- Tx Buffer Transmission Occurred
- Txefa
- Tx Event FIFO Acknowledge
- Txefc
- Tx Event FIFO Configuration
- Txefs
- Tx Event FIFO Status
- Txesc
- Tx Buffer Element Size Configuration
- Txfqs
- Tx FIFO/Queue Status
- Xidam
- Extended ID AND Mask
- Xidfc
- Extended ID Filter Configuration