Module regs 

Structs

BaseAddr0

Base Address for region 0 register.

BaseAddr1

Base Address for region 1 register.

BaseAddr2

Base Address for region 2 register.

EncEnable

Encryption Enable register.

Err

Error status register.

IvLsb0

Initial Vector register for region 0, Least Significant Bits.

IvLsb1

Initial Vector register for region 1, Least Significant Bits.

IvLsb2

Initial Vector register for region 2, Least Significant Bits.

IvMsb0

Initial Vector register for region 0, Most Significant Bits.

IvMsb1

Initial Vector register for region 1, Most Significant Bits.

IvMsb2

Initial Vector register for region 2, Most Significant Bits.

Lock

Lock register.

MaskLsb

Data Mask register, 32 Least Significant Bits.

MaskMsb

Data Mask register, 32 Most Significant Bits.

SrEnable0

Sub-Region Enable register for region 0.

SrEnable1

Sub-Region Enable register for region 1.

SrEnable2

Sub-Region Enable register for region 2.