Structsยง
- Adcclkdiv
- ADC clock divider.
- Adcclksel
- ADC clock source select.
- Ahbclkctrl0
- AHB Clock control 0.
- Ahbclkctrl1
- AHB Clock control 1.
- Ahbclkctrl2
- AHB Clock control 2.
- Ahbclkctrlclr
- Peripheral reset control register.
- Ahbclkctrlset
- Peripheral reset control register.
- Ahbclkdiv
- System clock divider.
- Ahbmatprio
- AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest.
- Autoclkgateoverride
- Control automatic clock gating.
- Boot
Lock - Control write access to boot seed security registers.
- Boot
Seed Reg0 - boot seed (256-bit random value).
- Boot
Seed Reg1 - boot seed (256-bit random value).
- Boot
Seed Reg2 - boot seed (256-bit random value).
- Boot
Seed Reg3 - boot seed (256-bit random value).
- Boot
Seed Reg4 - boot seed (256-bit random value).
- Boot
Seed Reg5 - boot seed (256-bit random value).
- Boot
Seed Reg6 - boot seed (256-bit random value).
- Boot
Seed Reg7 - boot seed (256-bit random value).
- Canclkdiv
- CAN clock divider.
- Canclksel
- CAN clock source select.
- Casper
Ctrl - Control CASPER integration.
- Clk32kclksel
- clock low speed source select for HS USB.
- Clkoutdiv
- CLKOUT clock divider.
- Clkoutsel
- CLKOUT clock source select.
- Clock
Ctrl - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures.
- Clockgenupdatelockout
- Control clock configuration registers access (like xxxDIV, xxxSEL).
- Comp
IntCtrl - Comparator Interrupt control.
- Comp
IntStatus - Comparator Interrupt status.
- Cpstat
- CPU Status.
- Cpu0nstckcal
- System tick calibration for non-secure part of CPU0.
- Cpu0stckcal
- System tick calibration for secure part of CPU0.
- Ctimerclksel0
- CTimer 0 clock source select.
- Ctimerclksel1
- CTimer 1 clock source select.
- Ctimerclksel2
- CTimer 2 clock source select.
- Ctimerclksel3
- CTimer 3 clock source select.
- Ctimerclksel4
- CTimer 4 clock source select.
- Ctimerclkselx0
- Peripheral reset control register.
- Ctimerclkselx1
- Peripheral reset control register.
- Ctimerclkselx2
- Peripheral reset control register.
- Ctimerclkselx3
- Peripheral reset control register.
- Ctimerclkselx4
- Peripheral reset control register.
- Debug
Auth Beacon - Debug authentication BEACON register.
- Debug
Features - Cortex debug features control.
- Debug
Features Dp - Cortex debug features control. (duplicate).
- Debug
Lock En - Control write access to security registers.
- Device
Id0 - Device ID.
- Dieid
- Chip revision ID and Number.
- Fcclksel
- Flexcomm Interface 0 clock source select for Fractional Rate Divider.
- Fcclkselx
- Peripheral reset control register.
- Flashremap
Lock - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers.
- Flashremap
Offset - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB.
- Flashremap
Offset Dp - This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security.
- Flashremap
Size - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB.
- Flashremap
Size Dp - This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security.
- Flexfrgctrl
- Fractional rate divider for flexcomm 0.
- Flexfrgxctrl
- Peripheral reset control register.
- Fmccr
- FMC configuration register.
- Fmcflush
- FMCflush control.
- Fro1mclkdiv
- FRO1MHz Clock divider (FRO1M_divided).
- Frohfdiv
- FRO_HF (96MHz) clock divider.
- Funcretentionctrl
- Functional retention control register.
- Gpiopsync
- Enable bypass of the first stage of synchonization inside GPIO_INT module.
- Hashresthwkey
- Controls whether the HASH AES hardware secret key is restricted to use by secure code.
- Hmac
Reg0 - HMAC.
- Hmac
Reg1 - HMAC.
- Hmac
Reg2 - HMAC.
- Hmac
Reg3 - HMAC.
- Hmac
Reg4 - HMAC.
- Hmac
Reg5 - HMAC.
- Hmac
Reg6 - HMAC.
- Hmac
Reg7 - HMAC.
- Hslspiclksel
- HS LSPI clock source select.
- KeyBlock
- block quiddikey/PUF all index.
- Mainclksela
- Main clock A source select.
- Mainclkselb
- Main clock source select.
- Mclkclksel
- MCLK clock source select.
- Mclkdiv
- I2S MCLK clock divider.
- Mclkio
- MCLK control.
- Memoryremap
- Memory Remap control register.
- Nmisrc
- NMI Source Select.
- Pll0clkdiv
- PLL0 clock divider.
- Pll0clksel
- PLL0 clock source select.
- Pll0ctrl
- PLL0 550m control.
- Pll0ndec
- PLL0 550m N divider.
- Pll0pdec
- PLL0 550m P divider.
- Pll0sscg0
- PLL0 Spread Spectrum Wrapper control register 0.
- Pll0sscg1
- PLL0 Spread Spectrum Wrapper control register 1.
- Pll0stat
- PLL0 550m status.
- Pll1clksel
- PLL1 clock source select.
- Pll1ctrl
- PLL1 550m control.
- Pll1mdec
- PLL1 550m M divider.
- Pll1ndec
- PLL1 550m N divider.
- Pll1pdec
- PLL1 550m P divider.
- Pll1stat
- PLL1 550m status.
- Presetctrl0
- Peripheral reset control 0.
- Presetctrl1
- Peripheral reset control 1.
- Presetctrl2
- Peripheral reset control 2.
- Presetctrlclr
- Peripheral reset control clear register.
- Presetctrlset
- Peripheral reset control set register.
- Sctclkdiv
- SCT/PWM clock divider.
- Sctclksel
- SCTimer/PWM clock source select.
- SwdAccess
Cpu0 - This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0.
- SwrReset
- generate a software_reset.
- Systickclkdiv0
- System Tick Timer divider for CPU0.
- Systickclksel0
- System Tick Timer for CPU0 source select.
- Systickclkselx0
- Peripheral reset control register.
- Traceclkdiv
- TRACE clock divider.
- Traceclksel
- Trace clock source select.
- Usb0clkdiv
- USB0-FS Clock divider.
- Usb0clksel
- FS USB clock source select.
- Usb0needclkctrl
- USB0-FS need clock control.
- Usb0needclkstat
- USB0-FS need clock status.
- Usb1needclkctrl
- USB1-HS need clock control.
- Usb1needclkstat
- USB1-HS need clock status.
- Wdtclkdiv
- WDT clock divider.