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lpc55s69_cm33_core0

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Module regs

Module regs 

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Structsยง

Cmd
command register.
Dataw
data register, word 0-7; Memory data, or command parameter, or command result.
Event
event register.
IntClrEnable
Clear interrupt enable bits.
IntClrStatus
Clear interrupt status bits.
IntEnable
Interrupt enable bits.
IntSetEnable
Set interrupt enable bits.
IntSetStatus
Set interrupt status bits.
IntStatus
Interrupt status bits.
ModuleId
Controller+Memory module identification.
Starta
start (or only) address for next flash command.
Stopa
end address for next flash command, if command operates on address ranges.