Module regs
Source - Cfg1
- Configuration register 1 for the primary channel pair.
- Cfg2
- Configuration register 2 for the primary channel pair.
- Div
- Clock divider, used by all channel pairs.
- Fifocfg
- FIFO configuration and enable register.
- Fifointenclr
- FIFO interrupt enable clear (disable) and read register.
- Fifointenset
- FIFO interrupt enable set (enable) and read register.
- Fifointstat
- FIFO interrupt status register.
- Fiford
- FIFO read data.
- Fiford48h
- FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
- Fiford48hnopop
- FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
- Fifordnopop
- FIFO data read with no FIFO pop.
- Fifosize
- FIFO size register
- Fifostat
- FIFO status register.
- Fifotrig
- FIFO trigger settings for interrupt and DMA request.
- Fifowr
- FIFO write data.
- Fifowr48h
- FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
- Id
- I2S Module identification
- Stat
- Status register for the primary channel pair.