Module regs 

Structs

Dma0ItrigEna

Enable DMA0 triggers

Dma0ItrigEnaClr

Clear one or several bits in DMA0_ITRIG_ENA register

Dma0ItrigEnaSet

Set one or several bits in DMA0_ITRIG_ENA register

Dma0ItrigInmux

Trigger select register for DMA0 channel

Dma0OtrigInmux

DMA0 output trigger selection to become DMA0 trigger

Dma0ReqEna

Enable DMA0 requests

Dma0ReqEnaClr

Clear one or several bits in DMA0_REQ_ENA register

Dma0ReqEnaSet

Set one or several bits in DMA0_REQ_ENA register

Dma1ItrigEna

Enable DMA1 triggers

Dma1ItrigEnaClr

Clear one or several bits in DMA1_ITRIG_ENA register

Dma1ItrigEnaSet

Set one or several bits in DMA1_ITRIG_ENA register

Dma1ItrigInmux

Trigger select register for DMA1 channel

Dma1OtrigInmux

DMA1 output trigger selection to become DMA1 trigger

Dma1ReqEna

Enable DMA1 requests

Dma1ReqEnaClr

Clear one or several bits in DMA1_REQ_ENA register

Dma1ReqEnaSet

Set one or several bits in DMA1_REQ_ENA register

FreqmeasRef

Selection for frequency measurement reference clock

FreqmeasTarget

Selection for frequency measurement target clock

Pintsecsel

Pin interrupt secure select register

Pintsel

Pin interrupt select register

Sct0Inmux

Input mux register for SCT0 input

Timer0captsel

Capture select registers for TIMER0 inputs

Timer1captsel

Capture select registers for TIMER1 inputs

Timer2captsel

Capture select registers for TIMER2 inputs

Timer3captsel

Capture select registers for TIMER3 inputs

Timer4captsel

Capture select registers for TIMER4 inputs