Module regs 

Structs

Addr

Address register for automatic address matching.

Brg

Baud Rate Generator register. 16-bit integer baud rate divisor value.

Cfg

USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

Ctl

USART Control register. USART control settings that are more likely to change during operation.

Fifocfg

FIFO configuration and enable register.

Fifointenclr

FIFO interrupt enable clear (disable) and read register.

Fifointenset

FIFO interrupt enable set (enable) and read register.

Fifointstat

FIFO interrupt status register.

Fiford

FIFO read data.

Fifordnopop

FIFO data read with no FIFO pop.

Fifosize

FIFO size register

Fifostat

FIFO status register.

Fifotrig

FIFO trigger settings for interrupt and DMA request.

Fifowr

FIFO write data.

Id

Peripheral identification register.

Intenclr

Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

Intenset

Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Intstat

Interrupt status register. Reflects interrupts that are currently enabled.

Osr

Oversample selection register for asynchronous communication.

Stat

USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.