Module regs 

Structs

CalGar

Calibration General A-Side Registers

CalGbr

Calibration General B-Side Registers

Cfg

ADC Configuration Register

Cmdh1

ADC Command High Buffer Register

Cmdh2

ADC Command High Buffer Register

Cmdh3

ADC Command High Buffer Register

Cmdh4

ADC Command High Buffer Register

Cmdh5

ADC Command High Buffer Register

Cmdh6

ADC Command High Buffer Register

Cmdh7

ADC Command High Buffer Register

Cmdh8

ADC Command High Buffer Register

Cmdh9

ADC Command High Buffer Register

Cmdh10

ADC Command High Buffer Register

Cmdh11

ADC Command High Buffer Register

Cmdh12

ADC Command High Buffer Register

Cmdh13

ADC Command High Buffer Register

Cmdh14

ADC Command High Buffer Register

Cmdh15

ADC Command High Buffer Register

Cmdl1

ADC Command Low Buffer Register

Cmdl2

ADC Command Low Buffer Register

Cmdl3

ADC Command Low Buffer Register

Cmdl4

ADC Command Low Buffer Register

Cmdl5

ADC Command Low Buffer Register

Cmdl6

ADC Command Low Buffer Register

Cmdl7

ADC Command Low Buffer Register

Cmdl8

ADC Command Low Buffer Register

Cmdl9

ADC Command Low Buffer Register

Cmdl10

ADC Command Low Buffer Register

Cmdl11

ADC Command Low Buffer Register

Cmdl12

ADC Command Low Buffer Register

Cmdl13

ADC Command Low Buffer Register

Cmdl14

ADC Command Low Buffer Register

Cmdl15

ADC Command Low Buffer Register

Ctrl

ADC Control Register

Cv

Compare Value Register

De

DMA Enable Register

Fctrl

FIFO Control Register

Gcc

Gain Calibration Control

Gcr

Gain Calculation Result

Ie

Interrupt Enable Register

Ofstrim

ADC Offset Trim Register

Param

Parameter Register

Pause

ADC Pause Register

Resfifo

ADC Data Result FIFO Register

Stat

ADC Status Register

Swtrig

Software Trigger Register

Tctrl

Trigger Control Register

Tst

ADC Test Register

Tstat

Trigger Status Register

Verid

Version ID Register