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Module i3c

Module i3c 

Source
Expand description

Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))

Structs§

I3c
Improved Inter-Integrated Circuit.
Ibiext1
Extended IBI Data 1.
Ibiext2
Extended IBI Data 2.
Mconfig
Controller Configuration.
MconfigExt
Controller Extended Configuration.
Mctrl
Controller Control.
Mdatactrl
Controller Data Control.
Mdmactrl
Controller DMA Control.
Mdynaddr
Controller Dynamic Address.
Merrwarn
Controller Errors and Warnings.
Mibirules
Controller In-band Interrupt Registry and Rules.
Mintclr
Controller Interrupt Clear.
Mintmasked
Controller Interrupt Mask.
Mintset
Controller Interrupt Set.
Mrdatab
Controller Read Data Byte.
Mrdatah
Controller Read Data Halfword.
MrmsgDdr
Controller Read Message in DDR mode.
MrmsgSdr
Controller Read Message in SDR mode.
Mstatus
Controller Status.
Mwdatab
Controller Write Data Byte.
Mwdatab1
Controller Write Byte Data 1 (to Bus).
Mwdatabe
Controller Write Data Byte End.
Mwdatah
Controller Write Data Halfword.
Mwdatah1
Controller Write Halfword Data (to Bus).
Mwdatahe
Controller Write Data Halfword End.
MwmsgDdrControl
Controller Write Message in DDR mode: First Control Word.
MwmsgDdrControl2
Controller Write Message in DDR Mode Control 2.
MwmsgDdrData
Controller Write Message Data in DDR mode.
MwmsgSdrControl
Controller Write Message Control in SDR mode.
MwmsgSdrData
Controller Write Message Data in SDR mode.
Scapabilities
Target Capabilities.
Scapabilities2
Target Capabilities 2.
Sconfig
Target Configuration.
Sctrl
Target Control.
Sdatactrl
Target Data Control.
Sdmactrl
Target DMA Control.
Sdynaddr
Target Dynamic Address.
Serrwarn
Target Errors and Warnings.
Sid
Target Module ID.
Sidext
Target ID Extension.
Sidpartno
Target ID Part Number.
Sintclr
Target Interrupt Clear.
Sintmasked
Target Interrupt Mask.
Sintset
Target Interrupt Set.
Smapctrl0
Map Feature Control 0.
Smaxlimits
Target Maximum Limits.
Smsgmapaddr
Target Message Map Address.
Srdatab
Target Read Data Byte.
Srdatah
Target Read Data Halfword.
Sstatus
Target Status.
Stcclock
Target Time Control Clock.
Svendorid
Target Vendor ID.
Swdatab
Target Write Data Byte.
Swdatab1
Target Write Data Byte.
Swdatabe
Target Write Data Byte End.
Swdatah
Target Write Data Halfword.
Swdatah1
Target Write Data Halfword.
Swdatahe
Target Write Data Halfword End.

Enums§

Actstate
Cause
Ccchandle
Disto
Dma
Evdet
Extfifo
Fiforx
Fifotx
Group
Hdrsupp
Hjdis
Hkeep
I2c
I3cCasDel
I3cCasrDel
IbiMrHj
Ibidis
Ibiresp
Ibitype
Idena
Idreg
Int
Laststatic
Master
MctrlDir
MdatactrlRxtrig
MdatactrlTxtrig
MdmactrlDmafb
MdmactrlDmatb
MdmactrlDmawidth
Mrdis
Mstena
MwmsgSdrControlDir
Nobyte
Request
Saddr
ScapabilitiesTimectrl
SctrlEvent
SdatactrlRxempty
SdatactrlRxtrig
SdatactrlTxfull
SdatactrlTxtrig
SdmactrlDmafb
SdmactrlDmatb
SdmactrlDmawidth
SdynaddrDavalid
SstatusStart
SstatusTimectrl
SstatusTxnotfull
State
Stccch
Stmsg
Stnotstop
Streqrd
Streqwr
Type