Module regs
Source - Mccr0
- Controller Clock Configuration 0
- Mccr1
- Controller Clock Configuration 1
- Mcfgr0
- Controller Configuration 0
- Mcfgr1
- Controller Configuration 1
- Mcfgr2
- Controller Configuration 2
- Mcfgr3
- Controller Configuration 3
- Mcr
- Controller Control
- Mder
- Controller DMA Enable
- Mdmr
- Controller Data Match
- Mfcr
- Controller FIFO Control
- Mfsr
- Controller FIFO Status
- Mier
- Controller Interrupt Enable
- Mrdr
- Controller Receive Data
- Mrdror
- Controller Receive Data Read Only
- Msr
- Controller Status
- Mtdr
- Controller Transmit Data
- Param
- Parameter
- Samr
- Target Address Match
- Sasr
- Target Address Status
- Scfgr0
- Target Configuration 0
- Scfgr1
- Target Configuration 1
- Scfgr2
- Target Configuration 2
- Scr
- Target Control
- Sder
- Target DMA Enable
- Sier
- Target Interrupt Enable
- Srdr
- Target Receive Data
- Srdror
- Target Receive Data Read Only
- Ssr
- Target Status
- Star
- Target Transmit ACK
- Stdr
- Target Transmit Data
- Verid
- Version ID