Expand description
Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))
Structs§
- AhbPeripheral0mem
Rule1 - AHB Peripheral 0 Memory Rule 1.
- AhbPeripheral0mem
Rule2 - AHB Peripheral 0 Memory Rule 2.
- AhbPeripheral0mem
Rule3 - AHB Peripheral 0 Memory Rule 3.
- AhbPeripheral0mem
Rule4 - AHB Peripheral 0 Memory Rule 4.
- AhbPeripheral0mem
Rule5 - AHB Peripheral 0 Memory Rule 5.
- AhbSecure
Ctrl MemRule0 - AHB Secure Control Peripheral Rule.
- AhbSlave
Port P5slave Rule0 - AHB Slave Port 5 Rule Register.
- Ahbsc
- AHBSC.
- Aips
Bridge Group0mem Rule0 - AIPS Bridge Group 0 Memory Rule 0.
- Aips
Bridge Group0mem Rule1 - AIPS Bridge Group 0 Memory Rule 1.
- Aips
Bridge Group1mem Rule0 - AIPS Bridge Group 1 Memory Rule 0.
- Aips
Bridge Group1mem Rule1 - AIPS Bridge Group 1 Memory Rule 1.
- Aips
Bridge Group2mem Rule0 - AIPS Bridge Group 2 Rule 0.
- Aips
Bridge Group2mem Rule1 - AIPS Bridge Group 2 Rule 1.
- Aips
Bridge Group2mem Rule2 - AIPS Bridge Group 2 Rule 2.
- Aips
Bridge Group2mem Rule3 - AIPS Bridge Group 2 Rule 3.
- Aips
Bridge Group2mem Rule4 - AIPS Bridge Group 2 Rule 4.
- Aips
Bridge Group2mem Rule5 - AIPS Bridge Group 2 Rule 5.
- Aips
Bridge Group2mem Rule6 - AIPS Bridge Group 2 Rule 6.
- Aips
Bridge Group2mem Rule7 - AIPS Bridge Group 2 Rule 7.
- Aips
Bridge Group2mem Rule8 - AIPS Bridge Group 2 Rule 8.
- Aips
Bridge Group2mem Rule9 - AIPS Bridge Group 2 Rule 9.
- Aips
Bridge Group2mem Rule10 - AIPS Bridge Group 2 Rule 10.
- Aips
Bridge Group2mem Rule11 - AIPS Bridge Group 2 Rule 11.
- Aips
Bridge Group2mem Rule12 - AIPS Bridge Group 2 Rule 12.
- Aips
Bridge Group2mem Rule13 - AIPS Bridge Group 2 Rule 13.
- ApbPeripheral
Group0mem Rule0 - APB Bridge Group 0 Memory Rule Register 0.
- ApbPeripheral
Group0mem Rule1 - APB Bridge Group 0 Memory Rule Register 1.
- Cpu0lock
Reg - Miscellaneous CPU0 Control Signals.
- Flash00mem
Rule - Flash Memory Rule.
- Flash01mem
Rule - Flash Memory Rule.
- Flash02mem
Rule - Flash IFR0 Rule register.
- Flash03mem
Rule - Flash Memory Rule.
- Flexspi0region0mem
Rule - FLEXSPI0 Region 0 Memory Rule.
- Flexspi0region16mem
Rule - Array of registers: FLEXSPI0_REGION_MEM_RULE.
- Flexspi0region
MemRule - FLEXSPI0 Region index Memory Rule.
- Master
SecAnti PolReg - Master Secure Level.
- Master
SecLevel - Master Secure Level.
- Misc
Ctrl DpReg - Secure Control Duplicate.
- Misc
Ctrl Reg - Secure Control.
- RamMem
Rule - RAMA Memory Rule 0.
- RomMem
Rule - ROM Memory Rule.
- SecGp
Reg - Secure general purpose registers.
- SecVio
Addr - Security Violation Address.
- SecVio
Info Valid - Security Violation Info Validity for Address.
- SecVio
Misc Info - Security Violation Miscellaneous Information at Address.