Module regs
Source - Dmactrl
- DMA Control
- Espicap
- eSPI Capabilities
- Espicfg
- eSPI Configuration
- Espimisc
- eSPI Miscellaneous
- Intenclr
- Interrupt Clear
- Intenset
- Interrupt Enable Set
- Intstat
- Masked Interrupt Status
- Irqpush
- IRQ Push
- Mapbase
- Mapped Base
- Mctrl
- Master Control
- Mstat
- Master Status
- P0addr
- Port Address
- P0cfg
- Port Configuration
- P0datain
- Port Data Input
- P0dataout
- Port Data Out
- P0irulestat
- Set Interrupt Rules and User Status
- P0omflen
- Port OOB, Mastering, and Flash Length
- P0ramuse
- Port RAM Use
- P0stat
- Port Status
- P1addr
- Port Address
- P1cfg
- Port Configuration
- P1datain
- Port Data Input
- P1dataout
- Port Data Out
- P1irulestat
- Set Interrupt Rules and User Status
- P1omflen
- Port OOB, Mastering, and Flash Length
- P1ramuse
- Port RAM Use
- P1stat
- Port Status
- P2addr
- Port Address
- P2cfg
- Port Configuration
- P2datain
- Port Data Input
- P2dataout
- Port Data Out
- P2irulestat
- Set Interrupt Rules and User Status
- P2omflen
- Port OOB, Mastering, and Flash Length
- P2ramuse
- Port RAM Use
- P2stat
- Port Status
- P3addr
- Port Address
- P3cfg
- Port Configuration
- P3datain
- Port Data Input
- P3dataout
- Port Data Out
- P3irulestat
- Set Interrupt Rules and User Status
- P3omflen
- Port OOB, Mastering, and Flash Length
- P3ramuse
- Port RAM Use
- P3stat
- Port Status
- P4addr
- Port Address
- P4cfg
- Port Configuration
- P4datain
- Port Data Input
- P4dataout
- Port Data Out
- P4irulestat
- Set Interrupt Rules and User Status
- P4omflen
- Port OOB, Mastering, and Flash Length
- P4ramuse
- Port RAM Use
- P4stat
- Port Status
- P80stat
- Port 80 Status
- Rambase
- RAM Base
- RpmcSupport1
- RPMC Support 1
- RpmcSupport2
- RPMC Support 2
- Stataddr
- Status Block Address
- WireinGpio
- WIREIN_GPIO
- WireoutGpio
- WIREOUT_GPIO
- Wirero
- Virtual Wire Host-to-MCU
- Wirewo
- Virtual Wire MCU-to-host