Module regs 

Structs

CmpFuncClkdiv

CMP0_FUNC clock divider control

CmpRrClkdiv

CMP0_RR clock divider control

CmpRrClksel

CMP0_RR clock selection control

CtimerClkdiv

CTIMER0 clock divider control

CtimerClksel

CTIMER0 clock selection control

DacClkdiv

DAC0 clock divider control

DacClksel

DAC0 clock selection control

E158Clkdiv

E1588 clock divider control

E158Clksel

E1588 clock selection control

EspiClkdiv

ESPI0 clock divider control

EspiClksel

ESPI0 clock selection control

FlexcanClkdiv

FLEXCAN0 clock divider control

FlexcanClksel

FLEXCAN0 clock selection control

FlexioClkdiv

FLEXIO0 clock divider control

FlexioClksel

FLEXIO0 clock selection control

FlexspiClkdiv

FLEXSPI0 clock divider control

FlexspiClksel

FLEXSPI0 clock selection control

GlbCcClr

AHB Clock Control Clear 0

GlbCcSet

AHB Clock Control Set 0

GlbRstClr

Peripheral Reset Control Clear 0

GlbRstSet

Peripheral Reset Control Set 0

I3cFclkClkdiv

I3C0_FCLK clock divider control

I3cFclkClksel

I3C0_FCLK clock selection control

Lpi2cClkdiv

LPI2C0 clock divider control

Lpi2cClksel

LPI2C0 clock selection control

LpspiClkdiv

LPSPI0 clock divider control

LpspiClksel

LPSPI0 clock selection control

LptmrClkdiv

LPTMR0 clock divider control

LptmrClksel

LPTMR0 clock selection control

LpuartClkdiv

LPUART0 clock divider control

LpuartClksel

LPUART0 clock selection control

MrccAdcClkdiv

ADCx clock divider control

MrccAdcClksel

ADCx clock selection control

MrccClkoutClkdiv

CLKOUT clock divider control

MrccClkoutClksel

CLKOUT clock selection control

MrccDbgTraceClkdiv

DBG_TRACE clock divider control

MrccDbgTraceClksel

DBG_TRACE clock selection control

MrccGlbAcc0

Control Automatic Clock Gating 0

MrccGlbAcc1

Control Automatic Clock Gating 1

MrccGlbAcc2

Control Automatic Clock Gating 2

MrccGlbAcc3

Control Automatic Clock Gating 3

MrccGlbAcc4

Control Automatic Clock Gating 4

MrccGlbCc0

AHB Clock Control 0

MrccGlbCc1

AHB Clock Control 1

MrccGlbCc2

AHB Clock Control 2

MrccGlbCc3

AHB Clock Control 3

MrccGlbCc4

AHB Clock Control 4

MrccGlbPr0

Peripheral Enable Configuration 0. Reset on POR only.

MrccGlbPr1

Peripheral Enable Configuration 1. Reset on POR only.

MrccGlbPr2

Peripheral Enable Configuration 2. Reset on POR only.

MrccGlbPr3

Peripheral Enable Configuration 3. Reset on POR only.

MrccGlbPr4

Peripheral Enable Configuration 4. Reset on POR only.

MrccGlbRst0

Peripheral Reset Control 0

MrccGlbRst1

Peripheral Reset Control 1

MrccGlbRst2

Peripheral Reset Control 2

MrccGlbRst3

Peripheral Reset Control 3

MrccGlbRst4

Peripheral Reset Control 4

MrccRmiiClkdiv

RMII clock divider control

MrccRmiiClksel

RMII clock selection control

MrccSystickClkdiv

SYSTICK clock divider control

MrccSystickClksel

SYSTICK clock selection control

OstimerClksel

OSTIMER0 clock selection control

T1sClkdiv

T1S0 clock divider control

T1sClksel

T1S0 clock selection control

TsiClkdiv

TSI0 clock divider control

TsiClksel

TSI0 clock selection control

UsbClksel

USB1 clock selection control

UsbPhyClkdiv

USB1_PHY clock divider control

UsbPhyClksel

USB1_PHY clock selection control

WwdtClkdiv

WWDT0 clock divider control

WwdtClksel

WWDT1 clock selection control