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Module scg

Module scg 

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Expand description

Peripheral access API (generated using chiptool v0.1.0 (e5ab29f 2026-04-30))

Structs§

Apllcsr
APLL Control Status Register.
Apllctrl
APLL Control Register.
AplllockCnfg
APLL LOCK Configuration Register.
Apllmdiv
APLL M Divider Register.
Apllndiv
APLL N Divider Register.
Apllpdiv
APLL P Divider Register.
Apllsscg0
APLL Spread Spectrum Control 0 Register.
Apllsscg1
APLL Spread Spectrum Control 1 Register.
Apllsscgstat
APLL SSCG Status Register.
Apllstat
APLL Status Register.
Aplltestctrl
APLL Test Control Register.
Apllteststat
APLL Test Status Register.
Csr
Clock Status Register.
Firccfg
FIRC Configuration Register.
Firccsr
FIRC Control Status Register.
Fircstat
FIRC Auto-trimming Status Register.
Firctcfg
FIRC Trim Configuration Register.
Firctest
FIRC Test Register.
Firctrim
FIRC Trim Register.
Ldocsr
LDO Control and Status Register.
Ldotest
LDO Test Register.
Param
Parameter Register.
Rccr
Run Clock Control Register.
Rosccsr
ROSC Control Status Register.
Scg
System Clock Generator.
Sirccsr
SIRC Control Status Register.
Sircstat
SIRC Auto-trimming Status Register.
Sirctcfg
SIRC Trim Configuration Register.
Sirctest
SIRC Test Register.
Sirctrim
SIRC Trim Register.
Sosccfg
SOSC Configuration Register.
Sosccsr
SOSC Control Status Register.
Sosctest
SOSC Test Register.
Spllcsr
SPLL Control Status Register.
Spllctrl
SPLL Control Register.
SplllockCnfg
SPLL LOCK Configuration Register.
Spllmdiv
SPLL M Divider Register.
Spllndiv
SPLL N Divider Register.
Spllpdiv
SPLL P Divider Register.
Spllsscg0
SPLL Spread Spectrum Control 0 Register.
Spllsscg1
SPLL Spread Spectrum Control 1 Register.
Spllsscgstat
SPLL SSCG Status Register.
Spllstat
SPLL Status Register.
Splltestctrl
SPLL Test Control Register.
Spllteststat
SPLL Test Status Register.
TrimLock
Trim Lock register.
Upllcsr
UPLL Control Status Register.
Verid
Version ID Register.

Enums§

ApllLock
Apllcmre
ApllcsrLk
ApllctrlSource
Apllerr
Apllsscg1Mc
Apllsten
AplltestctrlTestvSel
ClkValid
Div16en
Erefs
Fircacc
FircaccIe
FirccsrLk
FirccsrTrimLock
Fircerr
FircerrIe
Fircsten
FirctcfgTrimsrc
Fircvld
FlipBufIn
FreqSel
IfrDisable
Overstress
Range
Rosccmre
RosccsrLk
Roscerr
Roscvld
Scs
SelAtx
SirccsrLk
SirccsrTrimLock
Sircerr
SircerrIe
SirctcfgTrimsrc
Sircvld
Sosccmre
SosccsrLk
Soscerr
Source
SpllLock
Spllcmre
SpllcsrLk
Spllerr
Spllsscg1Mc
Spllsten
SplltestctrlTestvSel
StartValid
TestBufBypass
TestBufEn
TestBufFlip
TestSel
Testen
Testsel
TrimUnlock
Tstmd
Upllcmre
UpllcsrLk
Upllerr
Upllvld
VoutSel