Structsยง
- AhbPeripheral0
Slave Port P12Slave Rule0 - AHB Peripheral 0 Slave Port 12 Slave Rule 0.
- AhbPeripheral0
Slave Port P12Slave Rule1 - AHB Peripheral 0 Slave Port 12 Slave Rule 1.
- AhbPeripheral0
Slave Port P12Slave Rule2 - AHB Peripheral 0 Slave Port 12 Slave Rule 2.
- AhbPeripheral1
Slave Port P13Slave Rule0 - AHB Peripheral 1 Slave Port 13 Slave Rule 0.
- AhbPeripheral1
Slave Port P13Slave Rule1 - AHB Peripheral 1 Slave Port 13 Slave Rule 1.
- AhbPeripheral1
Slave Port P13Slave Rule2 - AHB Peripheral 1 Slave Port 13 Slave Rule 2.
- AhbSecure
Ctrl Peripheral Rule0 - AHB Secure Control Peripheral Rule 0.
- Aips
Bridge Group0 MemRule0 - AIPS Bridge Group 0 Memory Rule 0.
- Aips
Bridge Group0 MemRule1 - AIPS Bridge Group 0 Memory Rule 1.
- Aips
Bridge Group0 MemRule2 - AIPS Bridge Group 0 Memory Rule 2.
- Aips
Bridge Group0 MemRule3 - AIPS Bridge Group 0 Memory Rule 3.
- Aips
Bridge Group1 MemRule0 - AIPS Bridge Group 1 Rule 0.
- Aips
Bridge Group1 MemRule1 - AIPS Bridge Group 1 Rule 1.
- Aips
Bridge Group2 MemRule0 - AIPS Bridge Group 2 Rule 0.
- Aips
Bridge Group2 MemRule1 - AIPS Bridge Group 2 Memory Rule 1.
- Aips
Bridge Group3 MemRule0 - AIPS Bridge Group 3 Rule 0.
- Aips
Bridge Group3 MemRule1 - AIPS Bridge Group 3 Memory Rule 1.
- Aips
Bridge Group3 MemRule2 - AIPS Bridge Group 3 Rule 2.
- Aips
Bridge Group3 MemRule3 - AIPS Bridge Group 3 Rule 3.
- Aips
Bridge Group4 MemRule0 - AIPS Bridge Group 4 Rule 0.
- Aips
Bridge Group4 MemRule1 - AIPS Bridge Group 4 Rule 1.
- Aips
Bridge Group4 MemRule2 - AIPS Bridge Group 4 Rule 2.
- Aips
Bridge Group4 MemRule3 - AIPS Bridge Group 4 Rule 3.
- ApbPeripheral
Group0 MemRule0 - APB Bridge Group 0 Memory Rule 0.
- ApbPeripheral
Group0 MemRule1 - APB Bridge Group 0 Memory Rule 1.
- ApbPeripheral
Group0 MemRule2 - APB Bridge Group 0 Rule 2.
- ApbPeripheral
Group0 MemRule3 - APB Bridge Group 0 Memory Rule 3.
- ApbPeripheral
Group1 MemRule0 - APB Bridge Group 1 Memory Rule 0.
- ApbPeripheral
Group1 MemRule1 - APB Bridge Group 1 Memory Rule 1.
- ApbPeripheral
Group1 MemRule2 - APB Bridge Group 1 Memory Rule 2.
- Cpu0
Lock Reg - Miscellaneous CPU0 Control Signals.
- Cpu1
Lock Reg - Miscellaneous CPU1 Control Signals.
- Flash00
MemRule - Flash Memory Rule.
- Flash01
MemRule - Flash Memory Rule.
- Flash02
MemRule - Flash Memory Rule.
- Flash03
MemRule - Flash Memory Rule.
- Flexspi0
Region0 MemRule - FLEXSPI0 Region 0 Memory Rule.
- Flexspi0
Region7 MemRule - FLEXSPI0 Region 7 Memory Rule.
- Flexspi0
Region16 MemRule Flexspi0 Region MemRule0 - FLEXSPI0 Region index Memory Rule 0.
- Flexspi0
Region813 MemRule Flexspi0 Region MemRule0 - FLEXSPI0 Region index Memory Rule 0.
- Master
SecAnti PolReg - Master Secure Level.
- Master
SecLevel - Master Secure Level.
- Misc
Ctrl DpReg - Secure Control Duplicate.
- Misc
Ctrl Reg - Secure Control.
- Rama
MemRule - RAMA Memory Rule 0.
- Ramb
MemRule - RAMB Memory Rule.
- Ramc
MemRule - RAMC Memory Rule.
- Ramd
MemRule - RAMD Memory Rule.
- Rame
MemRule - RAME Memory Rule.
- Ramf
MemRule - RAMF Memory Rule.
- Ramg
MemRule - RAMG Memory Rule.
- Ramh
MemRule - RAMH Memory Rule.
- Ramx
MemRule - RAMX Memory Rule.
- RomMem
Rule - ROM Memory Rule.
- SecCpu1
IntMask0 - Secure Interrupt Mask 0 for CPU1.
- SecCpu1
IntMask1 - Secure Interrupt Mask 1 for CPU1.
- SecCpu1
IntMask2 - Secure Interrupt Mask 2 for CPU1.
- SecCpu1
IntMask3 - Secure Interrupt Mask 3 for CPU1.
- SecCpu1
IntMask4 - Secure Interrupt Mask 4 for CPU1.
- SecGp
RegLock - Secure Mask Lock.
- SecGpio
Mask - GPIO Mask for Port index.
- SecVio
Addr - Security Violation Address.
- SecVio
Info Valid - Security Violation Info Validity for Address.
- SecVio
Misc Info - Security Violation Miscellaneous Information at Address.