Embassy
nxp-pac

Crates

git

Versions

mcxn947_cm33_core1

Flavors

Module vals

nxp_pac::ahbsc

Module vals 

Source

Enumsยง

Adc0
Adc1
AhbSecureCtrlPeripheralRule0Rule0
AhbSecureCtrlPeripheralRule0Rule1
AhbSecureCtrlPeripheralRule0Rule2
AhbSecureCtrlPeripheralRule0Rule3
ApbPeripheralGroup1MemRule1Pkc
ApbPeripheralGroup1MemRule2Smartdma
Atx0
Cache64Polsel0
Can0Rule0
Can0Rule1
Can0Rule2
Can0Rule3
Can1Rule0
Can1Rule1
Can1Rule2
Can1Rule3
Cdog0
Cdog1
Cm33LockRegLock
Cmp0
Cmp1
Cmp2
Coolflux
Cpu0LockRegLockNsMpu
Cpu0LockRegLockNsVtor
Cpu1LockRegLockNsMpu
Cpu1LockRegLockNsVtor
Crc
Ctimer0
Ctimer1
Ctimer2
Ctimer3
Ctimer4
Dac
Dac0
DebugMailbox
Digtmp
EDma0Ch0
EDma0Ch1
EDma0Ch2
EDma0Ch3
EDma0Ch4
EDma0Ch5
EDma0Ch6
EDma0Ch7
EDma0Ch8
EDma0Ch9
EDma0Ch10
EDma0Ch11
EDma0Ch12
EDma0Ch13
EDma0Ch14
EDma0Ch15
EDma0Mp
EDma1Ch0
EDma1Ch1
EDma1Ch2
EDma1Ch3
EDma1Ch4
EDma1Ch5
EDma1Ch6
EDma1Ch7
EDma1Ch8
EDma1Ch9
EDma1Ch10
EDma1Ch11
EDma1Ch12
EDma1Ch13
EDma1Ch14
EDma1Ch15
EDma1Mp
Eim0
Els
ElsAlias1
ElsAlias2
ElsAlias3
Emvsim0
Emvsim1
Enc
Enc1
Enet
Erm0
Evtg
Ewm0
Flash00MemRuleRule0
Flash00MemRuleRule1
Flash00MemRuleRule2
Flash00MemRuleRule3
Flash00MemRuleRule4
Flash00MemRuleRule5
Flash00MemRuleRule6
Flash00MemRuleRule7
Flash01MemRuleRule0
Flash01MemRuleRule1
Flash01MemRuleRule2
Flash01MemRuleRule3
Flash01MemRuleRule4
Flash01MemRuleRule5
Flash01MemRuleRule6
Flash01MemRuleRule7
Flash02MemRuleRule0
Flash02MemRuleRule1
Flash02MemRuleRule2
Flash02MemRuleRule3
Flash03MemRuleRule0
Flash03MemRuleRule1
Flash03MemRuleRule2
Flash03MemRuleRule3
Flash03MemRuleRule4
Flash03MemRuleRule5
Flash03MemRuleRule6
Flash03MemRuleRule7
Flexcomm4
Flexcomm5
Flexcomm6
Flexcomm7
Flexcomm8
Flexcomm9
Flexio
Flexspi
Flexspi0Region0MemRuleRule0
Flexspi0Region0MemRuleRule1
Flexspi0Region0MemRuleRule2
Flexspi0Region0MemRuleRule3
Flexspi0Region0MemRuleRule4
Flexspi0Region0MemRuleRule5
Flexspi0Region0MemRuleRule6
Flexspi0Region0MemRuleRule7
Flexspi0Region7MemRuleRule0
Flexspi0Region7MemRuleRule1
Flexspi0Region7MemRuleRule2
Flexspi0Region7MemRuleRule3
Flexspi0Region7MemRuleRule4
Flexspi0Region7MemRuleRule5
Flexspi0Region7MemRuleRule6
Flexspi0Region7MemRuleRule7
Flexspi0Region16MemRuleFlexspi0RegionMemRule0Rule0
Flexspi0Region16MemRuleFlexspi0RegionMemRule0Rule1
Flexspi0Region16MemRuleFlexspi0RegionMemRule0Rule2
Flexspi0Region16MemRuleFlexspi0RegionMemRule0Rule3
Flexspi0Region16MemRuleFlexspi0RegionMemRule0Rule4
Flexspi0Region16MemRuleFlexspi0RegionMemRule0Rule5
Flexspi0Region813MemRuleFlexspi0RegionMemRule0Rule0
Flexspi0Region813MemRuleFlexspi0RegionMemRule0Rule1
Flexspi0Region813MemRuleFlexspi0RegionMemRule0Rule2
Flexspi0Region813MemRuleFlexspi0RegionMemRule0Rule3
Flexspi0Region813MemRuleFlexspi0RegionMemRule0Rule4
Flexspi0Region813MemRuleFlexspi0RegionMemRule0Rule5
FlexspiCmx
Fmu0
FmuTest
Freqme0
Gdet
Gpio0Alias0
Gpio0Alias1
Gpio1Alias0
Gpio1Alias1
Gpio2Alias0
Gpio2Alias1
Gpio3Alias0
Gpio3Alias1
Gpio4Alias0
Gpio4Alias1
Gpio5Alias0
Gpio5Alias1
Hpdac0
I3c0
I3c1
Inputmux
Int0Mask
Int1Mask
Int2Mask
Int3Mask
Int4Mask
Int5Mask
Int6Mask
Int7Mask
Int8Mask
Int9Mask
Int10Mask
Int11Mask
Int12Mask
Int13Mask
Int14Mask
Int15Mask
Int16Mask
Int17Mask
Int18Mask
Int19Mask
Int20Mask
Int21Mask
Int22Mask
Int23Mask
Int24Mask
Int25Mask
Int26Mask
Int27Mask
Int28Mask
Int29Mask
Int30Mask
Int31Mask
Int32Mask
Int33Mask
Int34Mask
Int35Mask
Int36Mask
Int37Mask
Int38Mask
Int39Mask
Int40Mask
Int41Mask
Int42Mask
Int43Mask
Int44Mask
Int45Mask
Int46Mask
Int47Mask
Int48Mask
Int49Mask
Int50Mask
Int51Mask
Int52Mask
Int53Mask
Int54Mask
Int55Mask
Int56Mask
Int57Mask
Int58Mask
Int59Mask
Int60Mask
Int61Mask
Int62Mask
Int63Mask
Int64Mask
Int65Mask
Int66Mask
Int67Mask
Int68Mask
Int69Mask
Int70Mask
Int71Mask
Int72Mask
Int73Mask
Int74Mask
Int75Mask
Int76Mask
Int77Mask
Int78Mask
Int79Mask
Int80Mask
Int81Mask
Int82Mask
Int83Mask
Int84Mask
Int85Mask
Int86Mask
Int87Mask
Int88Mask
Int89Mask
Int90Mask
Int91Mask
Int92Mask
Int93Mask
Int94Mask
Int95Mask
Int96Mask
Int97Mask
Int98Mask
Int99Mask
Int100Mask
Int101Mask
Int102Mask
Int103Mask
Int104Mask
Int105Mask
Int106Mask
Int107Mask
Int108Mask
Int109Mask
Int110Mask
Int111Mask
Int112Mask
Int113Mask
Int114Mask
Int115Mask
Int116Mask
Int117Mask
Int118Mask
Int119Mask
Int120Mask
Int121Mask
Int122Mask
Int123Mask
Int124Mask
Int125Mask
Int126Mask
Int127Mask
Int128Mask
Int129Mask
Int130Mask
Int131Mask
Int132Mask
Int133Mask
Int134Mask
Int135Mask
Int136Mask
Int137Mask
Int138Mask
Int139Mask
Int140Mask
Int141Mask
Int142Mask
Int143Mask
Int144Mask
Int145Mask
Int146Mask
Int147Mask
Int148Mask
Int149Mask
Int150Mask
Int151Mask
Int152Mask
Int153Mask
Int154Mask
Int155Mask
Int156Mask
Int157Mask
Int158Mask
Int159Mask
Intm0
Itrc
LockSMpu
LockSVtaircr
LockSau
LpFlexcomm0
LpFlexcomm1
LpFlexcomm2
LpFlexcomm3
Lpcac
Lptmr0
Lptmr1
Mailbox
MasterSecAntiPolRegCoolfluxi
MasterSecAntiPolRegCpu1
MasterSecAntiPolRegEDma0
MasterSecAntiPolRegEDma1
MasterSecAntiPolRegEthernet
MasterSecAntiPolRegNpuo
MasterSecAntiPolRegPkc
MasterSecAntiPolRegPq
MasterSecAntiPolRegSmartdma
MasterSecAntiPolRegUsbFs
MasterSecAntiPolRegUsbHs
MasterSecAntiPolRegUsdhc
MasterSecLevelAntipolLock
MasterSecLevelCoolfluxi
MasterSecLevelCpu1
MasterSecLevelEDma0
MasterSecLevelEDma1
MasterSecLevelEthernet
MasterSecLevelLock
MasterSecLevelNpuo
MasterSecLevelPkc
MasterSecLevelPq
MasterSecLevelSmartdma
MasterSecLevelUsbFs
MasterSecLevelUsbHs
MasterSecLevelUsdhc
Mbc
Micd
MiscCtrlDpRegDisableStrictMode
MiscCtrlDpRegDisableViolationAbort
MiscCtrlDpRegEnableNsPrivCheck
MiscCtrlDpRegEnableSPrivCheck
MiscCtrlDpRegEnableSecureChecking
MiscCtrlDpRegIdauAllNs
MiscCtrlDpRegWriteLock
MiscCtrlRegDisableStrictMode
MiscCtrlRegDisableViolationAbort
MiscCtrlRegEnableNsPrivCheck
MiscCtrlRegEnableSPrivCheck
MiscCtrlRegEnableSecureChecking
MiscCtrlRegIdauAllNs
MiscCtrlRegWriteLock
Mrt0
Mtr0
Npu
Npx
Opamp0
Opamp1
Opamp2
Ostimer0
Otpc
Pint0
Pio0Pin0SecMask
Pio0Pin1SecMask
Pio0Pin2SecMask
Pio0Pin3SecMask
Pio0Pin4SecMask
Pio0Pin5SecMask
Pio0Pin6SecMask
Pio0Pin7SecMask
Pio0Pin8SecMask
Pio0Pin9SecMask
Pio0Pin10SecMask
Pio0Pin11SecMask
Pio0Pin12SecMask
Pio0Pin13SecMask
Pio0Pin14SecMask
Pio0Pin15SecMask
Pio0Pin16SecMask
Pio0Pin17SecMask
Pio0Pin18SecMask
Pio0Pin19SecMask
Pio0Pin20SecMask
Pio0Pin21SecMask
Pio0Pin22SecMask
Pio0Pin23SecMask
Pio0Pin24SecMask
Pio0Pin25SecMask
Pio0Pin26SecMask
Pio0Pin27SecMask
Pio0Pin28SecMask
Pio0Pin29SecMask
Pio0Pin30SecMask
Pio0Pin31SecMask
PkcRam
Plu
Port0
Port1
Port2
Port3
Port4
Port5
Powerquad
PufAlias0
PufAlias1
PufAlias2
PufAlias3
Pwm
Pwm1
RamaMemRuleRule0
RamaMemRuleRule1
RamaMemRuleRule2
RamaMemRuleRule3
RamaMemRuleRule4
RamaMemRuleRule5
RamaMemRuleRule6
RamaMemRuleRule7
RambMemRuleRule0
RambMemRuleRule1
RambMemRuleRule2
RambMemRuleRule3
RambMemRuleRule4
RambMemRuleRule5
RambMemRuleRule6
RambMemRuleRule7
RamcMemRuleRule0
RamcMemRuleRule1
RamcMemRuleRule2
RamcMemRuleRule3
RamcMemRuleRule4
RamcMemRuleRule5
RamcMemRuleRule6
RamcMemRuleRule7
RamdMemRuleRule0
RamdMemRuleRule1
RamdMemRuleRule2
RamdMemRuleRule3
RamdMemRuleRule4
RamdMemRuleRule5
RamdMemRuleRule6
RamdMemRuleRule7
RameMemRuleRule0
RameMemRuleRule1
RameMemRuleRule2
RameMemRuleRule3
RameMemRuleRule4
RameMemRuleRule5
RameMemRuleRule6
RameMemRuleRule7
RamfMemRuleRule0
RamfMemRuleRule1
RamfMemRuleRule2
RamfMemRuleRule3
RamfMemRuleRule4
RamfMemRuleRule5
RamfMemRuleRule6
RamfMemRuleRule7
RamgMemRuleRule0
RamgMemRuleRule1
RamgMemRuleRule2
RamgMemRuleRule3
RamgMemRuleRule4
RamgMemRuleRule5
RamgMemRuleRule6
RamgMemRuleRule7
RamhMemRuleRule0
RamhMemRuleRule1
RamhMemRuleRule2
RamhMemRuleRule3
RamhMemRuleRule4
RamhMemRuleRule5
RamhMemRuleRule6
RamhMemRuleRule7
RamxMemRuleRule0
RamxMemRuleRule1
RamxMemRuleRule2
RamxMemRuleRule3
RamxMemRuleRule4
RamxMemRuleRule5
RamxMemRuleRule6
RamxMemRuleRule7
RomMemRuleRule0
RomMemRuleRule1
RomMemRuleRule2
RomMemRuleRule3
RomMemRuleRule4
RomMemRuleRule5
RomMemRuleRule6
RomMemRuleRule7
Rtc
Sai0
Sai1
Scg0
Sct0
SecCpu1IntMask0Lock
SecCpu1IntMask1Lock
SecCpu1IntMask2Lock
SecCpu1IntMask3Lock
SecCpu1IntMask4Lock
SecGpioMask0Lock
SecGpioMask1Lock
SecVioInfoDataAccess
SecVioInfoMaster
SecVioInfoWrite
Sema42
Sfa
Sinc0
Sm3
Spc0
Syscon
Trng
Tro0
Tsi
USdhc0
UsbFsOtgRam
Usbdcd
Usbfs
Usbhs
Usbhsphy
Utcik0
Vbat
Vref
Wuu0
Wwdt0
Wwdt1