Module regs 

Structs

DmaCh0Control

DMA Channel 0 Control

DmaCh0CurrentAppRxbuffer

Channel 0 Current Application Receive Buffer Address

DmaCh0CurrentAppRxdesc

Channel 0 Current Application Receive Descriptor

DmaCh0CurrentAppTxbuffer

Channel 0 Current Application Transmit Buffer Address

DmaCh0CurrentAppTxdesc

Channel 0 Current Application Transmit Descriptor

DmaCh0InterruptEnable

Channeli Interrupt Enable

DmaCh0MissFrameCnt

Channel 0 Missed Frame Counter

DmaCh0RxControl

DMA Channel 0 Receive Control

DmaCh0RxControl2

Channeli Receive Control

DmaCh0RxEriCnt

Channel 0 Receive ERI Counter

DmaCh0RxInterruptWatchdogTimer

Channel 0 Receive Interrupt Watchdog Timer

DmaCh0RxdescListAddress

Channel 0 Rx Descriptor List Address register

DmaCh0RxdescTailPointer

Channel 0 Rx Descriptor Tail Pointer

DmaCh0SlotFunctionControlStatus

Channel 0 Slot Function Control and Status

DmaCh0Status

DMA Channel 0 Status

DmaCh0TxControl

DMA Channel 0 Transmit Control

DmaCh0TxdescListAddress

Channel 0 Tx Descriptor List Address register

DmaCh0TxdescRingLength

Channel 0 Tx Descriptor Ring Length

DmaCh0TxdescTailPointer

Channel 0 Tx Descriptor Tail Pointer

DmaCh1Control

DMA Channel 1 Control

DmaCh1CurrentAppRxbuffer

Channel 1 Current Application Receive Buffer Address

DmaCh1CurrentAppRxdesc

Channel 1 Current Application Receive Descriptor

DmaCh1CurrentAppTxbuffer

Channel 1 Current Application Transmit Buffer Address

DmaCh1CurrentAppTxdesc

Channel 1 Current Application Transmit Descriptor

DmaCh1InterruptEnable

Channel 1 Interrupt Enable

DmaCh1MissFrameCnt

Channel 1 Missed Frame Counter

DmaCh1RxControl

DMA Channel 1 Receive Control

DmaCh1RxControl2

DMA Channel 1 Receive Control

DmaCh1RxEriCnt

Channel 1 Receive ERI Counter

DmaCh1RxInterruptWatchdogTimer

Channel 1 Receive Interrupt Watchdog Timer

DmaCh1RxdescListAddress

Channel 1 Rx Descriptor List Address

DmaCh1RxdescTailPointer

Channel 1 Rx Descriptor Tail Pointer

DmaCh1SlotFunctionControlStatus

Channel 1 Slot Function Control and Status

DmaCh1Status

DMA Channel 1 Status

DmaCh1TxControl

DMA Channel 1 Transmit Control

DmaCh1TxdescListAddress

Channel 1 Tx Descriptor List Address

DmaCh1TxdescRingLength

Channel 1 Tx Descriptor Ring Length

DmaCh1TxdescTailPointer

Channel 1 Tx Descriptor Tail Pointer

DmaDebugStatus0

DMA Debug Status 0

DmaInterruptStatus

DMA Interrupt Status

DmaMode

DMA Bus Mode

DmaSysbusMode

DMA System Bus Mode

IndirAccessCtrl

Indirect Access Control

IndirAccessData

Indirect Access Data

MacAddress0High

MAC Address0 High

MacAddress0Low

MAC Address0 Low

MacConfiguration

MAC Configuration

MacCsrSwCtrl

CSR Software Control

MacDebug

MAC Debug

MacExtConfiguration

MAC Extended Configuration Register

MacHwFeature0

Hardware Features 0

MacHwFeature1

Hardware Features 1

MacHwFeature2

Hardware Features 2

MacHwFeature3

Hardware Features 3

MacInnerVlanIncl

MAC Inner VLAN Tag Inclusion or Replacement

MacInterruptEnable

Interrupt Enable

MacInterruptStatus

Interrupt Status

MacLpiControlStatus

LPI Control and Status

MacLpiEntryTimer

Tx LPI Entry Timer Control

MacLpiTimersControl

LPI Timers Control

MacMdioAddress

MDIO Address

MacMdioData

MAC MDIO Data

MacOneusTicCounter

One-microsecond Reference Timer

MacPacketFilter

MAC Packet Filter

MacPmtControlStatus

PMT Control and Status

MacPpsControl

PPS Control

MacQ0TxFlowCtrl

MAC Q0 Tx Flow Control

MacRwkPacketFilter

Remote Wakeup Filter

MacRxFlowCtrl

MAC Rx Flow Control

MacRxTxStatus

Receive Transmit Status

MacRxqCtrl0

Receive Queue Control 0

MacRxqCtrl1

Receive Queue Control 1

MacRxqCtrl2

Receive Queue Control 2

MacRxqCtrl4

Receive Queue Control 4

MacSubSecondIncrement

Subsecond Increment

MacSystemTimeNanoseconds

System Time Nanoseconds

MacSystemTimeNanosecondsUpdate

System Time Nanoseconds Update

MacSystemTimeSeconds

System Time Seconds

MacSystemTimeSecondsUpdate

System Time Seconds Update

MacTimestampAddend

Timestamp Addend

MacTimestampControl

Timestamp Control

MacTimestampEgressCorrNanosecond

Timestamp Egress Correction Nanosecond

MacTimestampEgressLatency

Timestamp Egress Latency

MacTimestampIngressCorrNanosecond

Timestamp Ingress Correction Nanosecond

MacTimestampIngressLatency

Timestamp Ingress Latency

MacTimestampStatus

Timestamp Status

MacTxTimestampStatusNanoseconds

Transmit Timestamp Status Nanoseconds

MacTxTimestampStatusSeconds

Transmit Timestamp Status Seconds

MacVersion

MAC Version

MacVlanIncl

VLAN Tag Inclusion or Replacement

MacVlanTagCtrl

MAC VLAN Tag Control

MacWatchdogTimeout

Watchdog Timeout

MtlInterruptStatus

MTL Interrupt Status

MtlOperationMode

MTL Operation Mode

MtlQ0InterruptControlStatus

Queue 0 Interrupt Control Status

MtlQ1InterruptControlStatus

Queue 1 Interrupt Control Status

MtlRxq0Control

Queue 0 Receive Control

MtlRxq0Debug

Queue 0 Receive Debug

MtlRxq0MissedPacketOverflowCnt

Queue 0 Missed Packet and Overflow Counter

MtlRxq0OperationMode

Queue 0 Receive Operation Mode

MtlRxq1Control

Queue 1 Receive Control

MtlRxq1Debug

Queue 1 Receive Debug

MtlRxq1MissedPacketOverflowCnt

Queue 1 Missed Packet and Overflow Counter

MtlRxq1OperationMode

Queue 1 Receive Operation Mode

MtlRxqDmaMap0

Receive Queue and DMA Channel Mapping 0

MtlTxq0Debug

Queue 0 Transmit Debug

MtlTxq0EtsStatus

Queue 0 ETS Status

MtlTxq0OperationMode

Queue 0 Transmit Operation Mode

MtlTxq0QuantumWeight

Queue 0 Quantum or Weights

MtlTxq0Underflow

Queue 0 Underflow Counter

MtlTxq1Debug

Queue 1 Transmit Debug

MtlTxq1EtsControl

Queue 1 ETS Control

MtlTxq1EtsStatus

Queue 1 ETS Status

MtlTxq1Hicredit

Queue 1 hiCredit

MtlTxq1Locredit

Queue 1 loCredit

MtlTxq1OperationMode

Queue 1 Transmit Operation Mode

MtlTxq1QuantumWeight

Queue 1 idleSlopeCredit, Quantum or Weights

MtlTxq1Sendslopecredit

Queue 1 sendSlopeCredit

MtlTxq1Underflow

Queue 1 Underflow Counter

Pps0TargetTimeNanoseconds

PPS0 Target Time Nanoseconds

Pps0TargetTimeSeconds

PPS0 Target Time Seconds