Module regs
Source - Ctrl
- USB PHY General Control Register
- CtrlClr
- USB PHY General Control Register
- CtrlSet
- USB PHY General Control Register
- CtrlTog
- USB PHY General Control Register
- Debug
- USB PHY Debug Register
- Debug0Status
- UTMI Debug Status Register 0
- Debug1
- UTMI Debug Status Register 1
- Debug1Clr
- UTMI Debug Status Register 1
- Debug1Set
- UTMI Debug Status Register 1
- Debug1Tog
- UTMI Debug Status Register 1
- DebugClr
- USB PHY Debug Register
- DebugSet
- USB PHY Debug Register
- DebugTog
- USB PHY Debug Register
- Pwd
- USB PHY Power-Down Register
- PwdClr
- USB PHY Power-Down Register
- PwdSet
- USB PHY Power-Down Register
- PwdTog
- USB PHY Power-Down Register
- Rx
- USB PHY Receiver Control Register
- RxClr
- USB PHY Receiver Control Register
- RxSet
- USB PHY Receiver Control Register
- RxTog
- USB PHY Receiver Control Register
- Status
- USB PHY Status Register
- Tx
- USB PHY Transmitter Control Register
- TxClr
- USB PHY Transmitter Control Register
- TxSet
- USB PHY Transmitter Control Register
- TxTog
- USB PHY Transmitter Control Register
- Version
- UTMI RTL Version