Enumsยง
- Misc0
Clkgate Ctrl - Misc0
Clkgate Delay - Misc0
ClrClkgate Ctrl - Misc0
ClrClkgate Delay - Misc0
ClrDiscon High Snvs - Misc0
ClrOscI - Misc0
ClrReftop Selfbiasoff - Misc0
ClrReftop Vbgadj - Misc0
ClrRtc Xtal Source - Misc0
ClrStop Mode Config - Misc0
ClrVid PllPrediv - Misc0
Discon High Snvs - Misc0
OscI - Misc0
Reftop Selfbiasoff - Misc0
Reftop Vbgadj - Misc0
RtcXtal Source - Misc0
SetClkgate Ctrl - Misc0
SetClkgate Delay - Misc0
SetDiscon High Snvs - Misc0
SetOscI - Misc0
SetReftop Selfbiasoff - Misc0
SetReftop Vbgadj - Misc0
SetRtc Xtal Source - Misc0
SetStop Mode Config - Misc0
SetVid PllPrediv - Misc0
Stop Mode Config - Misc0
TogClkgate Ctrl - Misc0
TogClkgate Delay - Misc0
TogDiscon High Snvs - Misc0
TogOscI - Misc0
TogReftop Selfbiasoff - Misc0
TogReftop Vbgadj - Misc0
TogRtc Xtal Source - Misc0
TogStop Mode Config - Misc0
TogVid PllPrediv - Misc0
VidPll Prediv - Misc1
ClrLvds1 ClkSel - Misc1
ClrLvds2 ClkSel - Misc1
Lvds1 ClkSel - Misc1
Lvds2 ClkSel - Misc1
SetLvds1 ClkSel - Misc1
SetLvds2 ClkSel - Misc1
TogLvds1 ClkSel - Misc1
TogLvds2 ClkSel - Misc2
Audio DivLsb - Misc2
Audio DivMsb - Misc2
ClrAudio DivLsb - Misc2
ClrAudio DivMsb - Misc2
ClrReg0 BoOffset - Misc2
ClrReg0 Step Time - Misc2
ClrReg1 BoOffset - Misc2
ClrReg1 Step Time - Misc2
ClrReg2 BoOffset - Misc2
ClrReg2 Step Time - Misc2
ClrVideo Div - Misc2
Reg0 BoOffset - Misc2
Reg0 Step Time - Misc2
Reg1 BoOffset - Misc2
Reg1 Step Time - Misc2
Reg2 BoOffset - Misc2
Reg2 Step Time - Misc2
SetAudio DivLsb - Misc2
SetAudio DivMsb - Misc2
SetReg0 BoOffset - Misc2
SetReg0 Step Time - Misc2
SetReg1 BoOffset - Misc2
SetReg1 Step Time - Misc2
SetReg2 BoOffset - Misc2
SetReg2 Step Time - Misc2
SetVideo Div - Misc2
TogAudio DivLsb - Misc2
TogAudio DivMsb - Misc2
TogReg0 BoOffset - Misc2
TogReg0 Step Time - Misc2
TogReg1 BoOffset - Misc2
TogReg1 Step Time - Misc2
TogReg2 BoOffset - Misc2
TogReg2 Step Time - Misc2
TogVideo Div - Misc2
Video Div - Reg1p1
ClrOutput Trg - Reg1p1
ClrSelref Weak Linreg - Reg1p1
Output Trg - Reg1p1
Selref Weak Linreg - Reg1p1
SetOutput Trg - Reg1p1
SetSelref Weak Linreg - Reg1p1
TogOutput Trg - Reg1p1
TogSelref Weak Linreg - Reg2p5
ClrOutput Trg - Reg2p5
Output Trg - Reg2p5
SetOutput Trg - Reg2p5
TogOutput Trg - Reg3p0
ClrOutput Trg - Reg3p0
ClrVbus Sel - Reg3p0
Output Trg - Reg3p0
SetOutput Trg - Reg3p0
SetVbus Sel - Reg3p0
TogOutput Trg - Reg3p0
TogVbus Sel - Reg3p0
Vbus Sel - RegCore
ClrRamp Rate - RegCore
ClrReg0 Adj - RegCore
ClrReg0 Targ - RegCore
ClrReg1 Adj - RegCore
ClrReg1 Targ - RegCore
ClrReg2 Adj - RegCore
ClrReg2 Targ - RegCore
Ramp Rate - RegCore
Reg0 Adj - RegCore
Reg0 Targ - RegCore
Reg1 Adj - RegCore
Reg1 Targ - RegCore
Reg2 Adj - RegCore
Reg2 Targ - RegCore
SetRamp Rate - RegCore
SetReg0 Adj - RegCore
SetReg0 Targ - RegCore
SetReg1 Adj - RegCore
SetReg1 Targ - RegCore
SetReg2 Adj - RegCore
SetReg2 Targ - RegCore
TogRamp Rate - RegCore
TogReg0 Adj - RegCore
TogReg0 Targ - RegCore
TogReg1 Adj - RegCore
TogReg1 Targ - RegCore
TogReg2 Adj - RegCore
TogReg2 Targ