Module regs
Source - Mccr0
- Master Clock Configuration 0
- Mccr1
- Master Clock Configuration 1
- Mcfgr0
- Master Configuration 0
- Mcfgr1
- Master Configuration 1
- Mcfgr2
- Master Configuration 2
- Mcfgr3
- Master Configuration 3
- Mcr
- Master Control
- Mder
- Master DMA Enable
- Mdmr
- Master Data Match
- Mfcr
- Master FIFO Control
- Mfsr
- Master FIFO Status
- Mier
- Master Interrupt Enable
- Mrdr
- Master Receive Data
- Msr
- Master Status
- Mtdr
- Master Transmit Data
- Param
- Parameter
- Samr
- Slave Address Match
- Sasr
- Slave Address Status
- Scfgr1
- Slave Configuration 1
- Scfgr2
- Slave Configuration 2
- Scr
- Slave Control
- Sder
- Slave DMA Enable
- Sier
- Slave Interrupt Enable
- Srdr
- Slave Receive Data
- Ssr
- Slave Status
- Star
- Slave Transmit ACK
- Stdr
- Slave Transmit Data
- Verid
- Version ID