Module regs
Source - Abort0
- Channel Abort control for all DMA channels.
- Abort1
- Channel Abort control for all DMA channels.
- Active0
- Channel Active status for all DMA channels.
- Active1
- Channel Active status for all DMA channels.
- Busy0
- Channel Busy status for all DMA channels.
- Busy1
- Channel Busy status for all DMA channels.
- Cfg
- Configuration register for DMA channel .
- Ctlstat
- Control and status register for DMA channel .
- Ctrl
- DMA control.
- Enableclr0
- Channel Enable Clear for all DMA channels.
- Enableclr1
- Channel Enable Clear for all DMA channels.
- Enableset0
- Channel Enable read and Set for all DMA channels.
- Enableset1
- Channel Enable read and Set for all DMA channels.
- Errint0
- Error Interrupt status for all DMA channels.
- Errint1
- Error Interrupt status for all DMA channels.
- Inta0
- Interrupt A status for all DMA channels.
- Inta1
- Interrupt A status for all DMA channels.
- Intb0
- Interrupt B status for all DMA channels.
- Intb1
- Interrupt B status for all DMA channels.
- Intenclr0
- Interrupt Enable Clear for all DMA channels.
- Intenclr1
- Interrupt Enable Clear for all DMA channels.
- Intenset0
- Interrupt Enable read and Set for all DMA channels.
- Intenset1
- Interrupt Enable read and Set for all DMA channels.
- Intstat
- Interrupt status.
- Settrig0
- Set Trigger control bits for all DMA channels.
- Settrig1
- Set Trigger control bits for all DMA channels.
- Setvalid0
- Set ValidPending control bits for all DMA channels.
- Setvalid1
- Set ValidPending control bits for all DMA channels.
- Srambase
- SRAM address of the channel configuration table.
- Xfercfg
- Transfer configuration register for DMA channel .