Structsยง
- Chanen
- Channel Enable register
- DcCtrl
- DC Filter Control
- Decreset
- no description available
- Divhfclk
- Divider for generating PDM clock from DMIC clock input
- Fifo
Ctrl - FIFO Control
- Fifo
Data - FIFO Data
- Fifo
Status - FIFO Status
- Gainshift
- Decimator output gain adjustment
- Global
Count Val - no description available
- Global
Sync En - global sync enable
- Hwvadgain
- HWVAD input gain register
- Hwvadhpfs
- HWVAD filter control register
- Hwvadlowz
- HWVAD noise envelope estimator register
- Hwvadrstt
- HWVAD filter reset register
- Hwvadst10
- HWVAD control register
- Hwvadthgn
- HWVAD noise estimator gain register
- Hwvadthgs
- HWVAD signal estimator gain register
- Osr
- CIC Filter decimation rate
- PhyCtrl
- Phy Ctrl
- Preac2fscoef
- Compensation filter for 2FS
- Preac4fscoef
- Compensation filter for 4FS
- Use2fs
- Use 2FS register