Module regs
Source - B
- Byte pin registers for all port 0 and 1 GPIO pins
- Clr
- Clear port
- Dir
- Direction registers
- Dirclr
- Clear pin direction bits for port
- Dirnot
- Toggle pin direction bits for port
- Dirset
- Set pin direction bits for port
- Intedg
- choose edge or level for interrupt
- Intena
- interrupt A enable control register
- Intenb
- interrupt B enable control register
- Intpol
- interupt polarity control register
- Intstata
- interrupt status for interrupt A
- Intstatb
- interrupt status for interrupt B
- Mask
- Mask register
- Mpin
- Masked port register
- Not
- Toggle port
- Pin
- Port pin register
- Set
- Write: Set register for port Read: output bits for port
- W
- Word pin registers for all port 0 and 1 GPIO pins