Enumsยง
- Adc
- Ahb2apb0
- Ahb2apb1
- AhbFlexspi
Access Disable - AhbSram
Access Disable Sram00 If - AhbSram
Access Disable Sram01 If - AhbSram
Access Disable Sram02 If - AhbSram
Access Disable Sram03 If - AhbSram
Access Disable Sram04 If - AhbSram
Access Disable Sram05 If - AhbSram
Access Disable Sram06 If - AhbSram
Access Disable Sram07 If - AhbSram
Access Disable Sram08 If - AhbSram
Access Disable Sram09 If - AhbSram
Access Disable Sram10 If - AhbSram
Access Disable Sram11 If - AhbSram
Access Disable Sram12 If - AhbSram
Access Disable Sram13 If - AhbSram
Access Disable Sram14 If - AhbSram
Access Disable Sram15 If - AhbSram
Access Disable Sram16 If - AhbSram
Access Disable Sram17 If - AhbSram
Access Disable Sram18 If - AhbSram
Access Disable Sram19 If - AhbSram
Access Disable Sram20 If - AhbSram
Access Disable Sram21 If - AhbSram
Access Disable Sram22 If - AhbSram
Access Disable Sram23 If - AhbSram
Access Disable Sram24 If - AhbSram
Access Disable Sram25 If - AhbSram
Access Disable Sram26 If - AhbSram
Access Disable Sram27 If - AhbSram
Access Disable Sram28 If - AhbSram
Access Disable Sram29 If - ApDev
Clk - ApHost
Clk - Autoclkgateoverride0
Dmac0 - Autoclkgateoverride0
Dmac1 - Casper
- Clkgateoverride0
Acmp - Clkgateoverride0
Mu - CrcEngine
- DbgFeatures
Dbgen - DbgFeatures
DpDbgen - DbgFeatures
DpNiden - DbgFeatures
DpSpiden - DbgFeatures
DpSpniden - DbgFeatures
Niden - DbgFeatures
Spiden - DbgFeatures
Spniden - DeepPd
- DevNeed
Clkst - DspFlexspi
Access Disable - DspSram
Access Disable Sram00 If - DspSram
Access Disable Sram01 If - DspSram
Access Disable Sram02 If - DspSram
Access Disable Sram03 If - DspSram
Access Disable Sram04 If - DspSram
Access Disable Sram05 If - DspSram
Access Disable Sram06 If - DspSram
Access Disable Sram07 If - DspSram
Access Disable Sram08 If - DspSram
Access Disable Sram09 If - DspSram
Access Disable Sram10 If - DspSram
Access Disable Sram11 If - DspSram
Access Disable Sram12 If - DspSram
Access Disable Sram13 If - DspSram
Access Disable Sram14 If - DspSram
Access Disable Sram15 If - DspSram
Access Disable Sram16 If - DspSram
Access Disable Sram17 If - DspSram
Access Disable Sram18 If - DspSram
Access Disable Sram19 If - DspSram
Access Disable Sram20 If - DspSram
Access Disable Sram21 If - DspSram
Access Disable Sram22 If - DspSram
Access Disable Sram23 If - DspSram
Access Disable Sram24 If - DspSram
Access Disable Sram25 If - DspSram
Access Disable Sram26 If - DspSram
Access Disable Sram27 If - DspSram
Access Disable Sram28 If - DspSram
Access Disable Sram29 If - Dspstall
- Fbbkeepst
- Host
Need Clkst - HsDev
WakeupN - Mainclk
Shutoff - Pdruncfg0
Acmp Pd - Pdruncfg0
AdcLp - Pdruncfg0
AdcPd - Pdruncfg0
Adctempsns Pd - Pdruncfg0
Audpllana Pd - Pdruncfg0
Audpllldo Pd - Pdruncfg0
ClrAcmp Pd - Pdruncfg0
ClrAdc Lp - Pdruncfg0
ClrAdc Pd - Pdruncfg0
ClrAdctempsns Pd - Pdruncfg0
ClrAudpllana Pd - Pdruncfg0
ClrAudpllldo Pd - Pdruncfg0
ClrFbb Pd - Pdruncfg0
ClrFfro Pd - Pdruncfg0
ClrHspad0 RefPd - Pdruncfg0
ClrHspad0 Vdet Lp - Pdruncfg0
ClrHspad2 RefPd - Pdruncfg0
ClrHspad2 Vdet Lp - Pdruncfg0
ClrHvd1v8 Pd - Pdruncfg0
ClrHvdcore Pd - Pdruncfg0
ClrLposc Pd - Pdruncfg0
ClrLvdcore Lp - Pdruncfg0
ClrPmcref Lp - Pdruncfg0
ClrPmic Mode0 - Pdruncfg0
ClrPmic Mode1 - Pdruncfg0
ClrPorcore Lp - Pdruncfg0
ClrRbb Pd - Pdruncfg0
ClrSfro Pd - Pdruncfg0
ClrSyspllana Pd - Pdruncfg0
ClrSyspllldo Pd - Pdruncfg0
ClrSysxtal Pd - Pdruncfg0
ClrVddcorereg Lp - Pdruncfg0
Ffro Pd - Pdruncfg0
Hspad0 RefPd - Pdruncfg0
Hspad0 Vdet Lp - Pdruncfg0
Hspad2 RefPd - Pdruncfg0
Hspad2 Vdet Lp - Pdruncfg0
Hvd1v8 Pd - Pdruncfg0
Hvdcore Pd - Pdruncfg0
Lposc Pd - Pdruncfg0
Lvdcore Lp - Pdruncfg0
Pmcref Lp - Pdruncfg0
Pmic Mode0 - Pdruncfg0
Pmic Mode1 - Pdruncfg0
Porcore Lp - Pdruncfg0
SetAcmp Pd - Pdruncfg0
SetAdc Lp - Pdruncfg0
SetAdc Pd - Pdruncfg0
SetAdctempsns Pd - Pdruncfg0
SetAudpllana Pd - Pdruncfg0
SetAudpllldo Pd - Pdruncfg0
SetFbb Pd - Pdruncfg0
SetFfro Pd - Pdruncfg0
SetHspad0 RefPd - Pdruncfg0
SetHspad0 Vdet Lp - Pdruncfg0
SetHspad2 RefPd - Pdruncfg0
SetHspad2 Vdet Lp - Pdruncfg0
SetHvd1v8 Pd - Pdruncfg0
SetHvdcore Pd - Pdruncfg0
SetLposc Pd - Pdruncfg0
SetLvdcore Lp - Pdruncfg0
SetPmcref Lp - Pdruncfg0
SetPmic Mode0 - Pdruncfg0
SetPmic Mode1 - Pdruncfg0
SetPorcore Lp - Pdruncfg0
SetRbb Pd - Pdruncfg0
SetSfro Pd - Pdruncfg0
SetSyspllana Pd - Pdruncfg0
SetSyspllldo Pd - Pdruncfg0
SetSysxtal Pd - Pdruncfg0
SetVddcorereg Lp - Pdruncfg0
Sfro Pd - Pdruncfg0
Syspllana Pd - Pdruncfg0
Syspllldo Pd - Pdruncfg0
Sysxtal Pd - Pdruncfg0
Vddcorereg Lp - Pdruncfg1
Casper Sram Apd - Pdruncfg1
Casper Sram Ppd - Pdruncfg1
ClrCasper Sram Apd - Pdruncfg1
ClrCasper Sram Ppd - Pdruncfg1
ClrDspcache Regf Apd - Pdruncfg1
ClrDspcache Regf Ppd - Pdruncfg1
ClrDsptcm Regf Apd - Pdruncfg1
ClrDsptcm Regf Ppd - Pdruncfg1
ClrFlexspi Sram Apd - Pdruncfg1
ClrFlexspi Sram Ppd - Pdruncfg1
ClrPq Sram Apd - Pdruncfg1
ClrPq Sram Ppd - Pdruncfg1
ClrRom Pd - Pdruncfg1
ClrSram Sleep - Pdruncfg1
ClrUsbhs Sram Apd - Pdruncfg1
ClrUsbhs Sram Ppd - Pdruncfg1
ClrUsdhc0 Sram Apd - Pdruncfg1
ClrUsdhc0 Sram Ppd - Pdruncfg1
ClrUsdhc1 Sram Apd - Pdruncfg1
ClrUsdhc1 Sram Ppd - Pdruncfg1
Dspcache Regf Apd - Pdruncfg1
Dspcache Regf Ppd - Pdruncfg1
Dsptcm Regf Apd - Pdruncfg1
Dsptcm Regf Ppd - Pdruncfg1
Flexspi Sram Apd - Pdruncfg1
Flexspi Sram Ppd - Pdruncfg1
PqSram Apd - Pdruncfg1
PqSram Ppd - Pdruncfg1
RomPd - Pdruncfg1
SetCasper Sram Apd - Pdruncfg1
SetCasper Sram Ppd - Pdruncfg1
SetDspcache Regf Apd - Pdruncfg1
SetDspcache Regf Ppd - Pdruncfg1
SetDsptcm Regf Apd - Pdruncfg1
SetDsptcm Regf Ppd - Pdruncfg1
SetFlexspi Sram Apd - Pdruncfg1
SetFlexspi Sram Ppd - Pdruncfg1
SetPq Sram Apd - Pdruncfg1
SetPq Sram Ppd - Pdruncfg1
SetRom Pd - Pdruncfg1
SetSram Sleep - Pdruncfg1
SetUsbhs Sram Apd - Pdruncfg1
SetUsbhs Sram Ppd - Pdruncfg1
SetUsdhc0 Sram Apd - Pdruncfg1
SetUsdhc0 Sram Ppd - Pdruncfg1
SetUsdhc1 Sram Apd - Pdruncfg1
SetUsdhc1 Sram Ppd - Pdruncfg1
Sram Sleep - Pdruncfg1
Usbhs Sram Apd - Pdruncfg1
Usbhs Sram Ppd - Pdruncfg1
Usdhc0 Sram Apd - Pdruncfg1
Usdhc0 Sram Ppd - Pdruncfg1
Usdhc1 Sram Apd - Pdruncfg1
Usdhc1 Sram Ppd - Pdruncfg2
ClrSram If0Apd - Pdruncfg2
ClrSram If1Apd - Pdruncfg2
ClrSram If2Apd - Pdruncfg2
ClrSram If3Apd - Pdruncfg2
ClrSram If4Apd - Pdruncfg2
ClrSram If5Apd - Pdruncfg2
ClrSram If6Apd - Pdruncfg2
ClrSram If7Apd - Pdruncfg2
ClrSram If8Apd - Pdruncfg2
ClrSram If9Apd - Pdruncfg2
ClrSram If10 Apd - Pdruncfg2
ClrSram If11 Apd - Pdruncfg2
ClrSram If12 Apd - Pdruncfg2
ClrSram If13 Apd - Pdruncfg2
ClrSram If14 Apd - Pdruncfg2
ClrSram If15 Apd - Pdruncfg2
ClrSram If16 Apd - Pdruncfg2
ClrSram If17 Apd - Pdruncfg2
ClrSram If18 Apd - Pdruncfg2
ClrSram If19 Apd - Pdruncfg2
ClrSram If20 Apd - Pdruncfg2
ClrSram If21 Apd - Pdruncfg2
ClrSram If22 Apd - Pdruncfg2
ClrSram If23 Apd - Pdruncfg2
ClrSram If24 Apd - Pdruncfg2
ClrSram If25 Apd - Pdruncfg2
ClrSram If26 Apd - Pdruncfg2
ClrSram If27 Apd - Pdruncfg2
ClrSram If28 Apd - Pdruncfg2
ClrSram If29 Apd - Pdruncfg2
SetSram If0Apd - Pdruncfg2
SetSram If1Apd - Pdruncfg2
SetSram If2Apd - Pdruncfg2
SetSram If3Apd - Pdruncfg2
SetSram If4Apd - Pdruncfg2
SetSram If5Apd - Pdruncfg2
SetSram If6Apd - Pdruncfg2
SetSram If7Apd - Pdruncfg2
SetSram If8Apd - Pdruncfg2
SetSram If9Apd - Pdruncfg2
SetSram If10 Apd - Pdruncfg2
SetSram If11 Apd - Pdruncfg2
SetSram If12 Apd - Pdruncfg2
SetSram If13 Apd - Pdruncfg2
SetSram If14 Apd - Pdruncfg2
SetSram If15 Apd - Pdruncfg2
SetSram If16 Apd - Pdruncfg2
SetSram If17 Apd - Pdruncfg2
SetSram If18 Apd - Pdruncfg2
SetSram If19 Apd - Pdruncfg2
SetSram If20 Apd - Pdruncfg2
SetSram If21 Apd - Pdruncfg2
SetSram If22 Apd - Pdruncfg2
SetSram If23 Apd - Pdruncfg2
SetSram If24 Apd - Pdruncfg2
SetSram If25 Apd - Pdruncfg2
SetSram If26 Apd - Pdruncfg2
SetSram If27 Apd - Pdruncfg2
SetSram If28 Apd - Pdruncfg2
SetSram If29 Apd - Pdruncfg2
Sram If0Apd - Pdruncfg2
Sram If1Apd - Pdruncfg2
Sram If2Apd - Pdruncfg2
Sram If3Apd - Pdruncfg2
Sram If4Apd - Pdruncfg2
Sram If5Apd - Pdruncfg2
Sram If6Apd - Pdruncfg2
Sram If7Apd - Pdruncfg2
Sram If8Apd - Pdruncfg2
Sram If9Apd - Pdruncfg2
Sram If10 Apd - Pdruncfg2
Sram If11 Apd - Pdruncfg2
Sram If12 Apd - Pdruncfg2
Sram If13 Apd - Pdruncfg2
Sram If14 Apd - Pdruncfg2
Sram If15 Apd - Pdruncfg2
Sram If16 Apd - Pdruncfg2
Sram If17 Apd - Pdruncfg2
Sram If18 Apd - Pdruncfg2
Sram If19 Apd - Pdruncfg2
Sram If20 Apd - Pdruncfg2
Sram If21 Apd - Pdruncfg2
Sram If22 Apd - Pdruncfg2
Sram If23 Apd - Pdruncfg2
Sram If24 Apd - Pdruncfg2
Sram If25 Apd - Pdruncfg2
Sram If26 Apd - Pdruncfg2
Sram If27 Apd - Pdruncfg2
Sram If28 Apd - Pdruncfg2
Sram If29 Apd - Pdruncfg3
ClrSram If0Ppd - Pdruncfg3
ClrSram If1Ppd - Pdruncfg3
ClrSram If2Ppd - Pdruncfg3
ClrSram If3Ppd - Pdruncfg3
ClrSram If4Ppd - Pdruncfg3
ClrSram If5Ppd - Pdruncfg3
ClrSram If6Ppd - Pdruncfg3
ClrSram If7Ppd - Pdruncfg3
ClrSram If8Ppd - Pdruncfg3
ClrSram If9Ppd - Pdruncfg3
ClrSram If10 Ppd - Pdruncfg3
ClrSram If11 Ppd - Pdruncfg3
ClrSram If12 Ppd - Pdruncfg3
ClrSram If13 Ppd - Pdruncfg3
ClrSram If14 Ppd - Pdruncfg3
ClrSram If15 Ppd - Pdruncfg3
ClrSram If16 Ppd - Pdruncfg3
ClrSram If17 Ppd - Pdruncfg3
ClrSram If18 Ppd - Pdruncfg3
ClrSram If19 Ppd - Pdruncfg3
ClrSram If20 Ppd - Pdruncfg3
ClrSram If21 Ppd - Pdruncfg3
ClrSram If22 Ppd - Pdruncfg3
ClrSram If23 Ppd - Pdruncfg3
ClrSram If24 Ppd - Pdruncfg3
ClrSram If25 Ppd - Pdruncfg3
ClrSram If26 Ppd - Pdruncfg3
ClrSram If27 Ppd - Pdruncfg3
ClrSram If28 Ppd - Pdruncfg3
ClrSram If29 Ppd - Pdruncfg3
SetSram If0Ppd - Pdruncfg3
SetSram If1Ppd - Pdruncfg3
SetSram If2Ppd - Pdruncfg3
SetSram If3Ppd - Pdruncfg3
SetSram If4Ppd - Pdruncfg3
SetSram If5Ppd - Pdruncfg3
SetSram If6Ppd - Pdruncfg3
SetSram If7Ppd - Pdruncfg3
SetSram If8Ppd - Pdruncfg3
SetSram If9Ppd - Pdruncfg3
SetSram If10 Ppd - Pdruncfg3
SetSram If11 Ppd - Pdruncfg3
SetSram If12 Ppd - Pdruncfg3
SetSram If13 Ppd - Pdruncfg3
SetSram If14 Ppd - Pdruncfg3
SetSram If15 Ppd - Pdruncfg3
SetSram If16 Ppd - Pdruncfg3
SetSram If17 Ppd - Pdruncfg3
SetSram If18 Ppd - Pdruncfg3
SetSram If19 Ppd - Pdruncfg3
SetSram If20 Ppd - Pdruncfg3
SetSram If21 Ppd - Pdruncfg3
SetSram If22 Ppd - Pdruncfg3
SetSram If23 Ppd - Pdruncfg3
SetSram If24 Ppd - Pdruncfg3
SetSram If25 Ppd - Pdruncfg3
SetSram If26 Ppd - Pdruncfg3
SetSram If27 Ppd - Pdruncfg3
SetSram If28 Ppd - Pdruncfg3
SetSram If29 Ppd - Pdruncfg3
Sram If0Ppd - Pdruncfg3
Sram If1Ppd - Pdruncfg3
Sram If2Ppd - Pdruncfg3
Sram If3Ppd - Pdruncfg3
Sram If4Ppd - Pdruncfg3
Sram If5Ppd - Pdruncfg3
Sram If6Ppd - Pdruncfg3
Sram If7Ppd - Pdruncfg3
Sram If8Ppd - Pdruncfg3
Sram If9Ppd - Pdruncfg3
Sram If10 Ppd - Pdruncfg3
Sram If11 Ppd - Pdruncfg3
Sram If12 Ppd - Pdruncfg3
Sram If13 Ppd - Pdruncfg3
Sram If14 Ppd - Pdruncfg3
Sram If15 Ppd - Pdruncfg3
Sram If16 Ppd - Pdruncfg3
Sram If17 Ppd - Pdruncfg3
Sram If18 Ppd - Pdruncfg3
Sram If19 Ppd - Pdruncfg3
Sram If20 Ppd - Pdruncfg3
Sram If21 Ppd - Pdruncfg3
Sram If22 Ppd - Pdruncfg3
Sram If23 Ppd - Pdruncfg3
Sram If24 Ppd - Pdruncfg3
Sram If25 Ppd - Pdruncfg3
Sram If26 Ppd - Pdruncfg3
Sram If27 Ppd - Pdruncfg3
Sram If28 Ppd - Pdruncfg3
Sram If29 Ppd - Pdsleepcfg0
Acmp Pd - Pdsleepcfg0
AdcLp - Pdsleepcfg0
AdcPd - Pdsleepcfg0
Adctempsns Pd - Pdsleepcfg0
Audpllana Pd - Pdsleepcfg0
Audpllldo Pd - Pdsleepcfg0
FbbPd - Pdsleepcfg0
Ffro Pd - Pdsleepcfg0
Hspad0 RefPd - Pdsleepcfg0
Hspad0 Vdet Lp - Pdsleepcfg0
Hspad2 RefPd - Pdsleepcfg0
Hspad2 Vdet Lp - Pdsleepcfg0
Hvd1v8 Pd - Pdsleepcfg0
Hvdcore Pd - Pdsleepcfg0
Lposc Pd - Pdsleepcfg0
Lvdcore Lp - Pdsleepcfg0
Pmcref Lp - Pdsleepcfg0
Pmic Mode0 - Pdsleepcfg0
Pmic Mode1 - Pdsleepcfg0
Porcore Lp - Pdsleepcfg0
RbbPd - Pdsleepcfg0
Sfro Pd - Pdsleepcfg0
Syspllana Pd - Pdsleepcfg0
Syspllldo Pd - Pdsleepcfg0
Sysxtal Pd - Pdsleepcfg0
Vddcorereg Lp - Pdsleepcfg1
Casper Sram Apd - Pdsleepcfg1
Casper Sram Ppd - Pdsleepcfg1
Dspcache Regf Apd - Pdsleepcfg1
Dspcache Regf Ppd - Pdsleepcfg1
Dsptcm Regf Apd - Pdsleepcfg1
Dsptcm Regf Ppd - Pdsleepcfg1
Flexspi Sram Apd - Pdsleepcfg1
Flexspi Sram Ppd - Pdsleepcfg1
PqSram Apd - Pdsleepcfg1
PqSram Ppd - Pdsleepcfg1
RomPd - Pdsleepcfg1
Sram Sleep - Pdsleepcfg1
Usbhs Sram Apd - Pdsleepcfg1
Usbhs Sram Ppd - Pdsleepcfg1
Usdhc0 Sram Apd - Pdsleepcfg1
Usdhc0 Sram Ppd - Pdsleepcfg1
Usdhc1 Sram Apd - Pdsleepcfg1
Usdhc1 Sram Ppd - Pdsleepcfg2
Sram If0Apd - Pdsleepcfg2
Sram If1Apd - Pdsleepcfg2
Sram If2Apd - Pdsleepcfg2
Sram If3Apd - Pdsleepcfg2
Sram If4Apd - Pdsleepcfg2
Sram If5Apd - Pdsleepcfg2
Sram If6Apd - Pdsleepcfg2
Sram If7Apd - Pdsleepcfg2
Sram If8Apd - Pdsleepcfg2
Sram If9Apd - Pdsleepcfg2
Sram If10 Apd - Pdsleepcfg2
Sram If11 Apd - Pdsleepcfg2
Sram If12 Apd - Pdsleepcfg2
Sram If13 Apd - Pdsleepcfg2
Sram If14 Apd - Pdsleepcfg2
Sram If15 Apd - Pdsleepcfg2
Sram If16 Apd - Pdsleepcfg2
Sram If17 Apd - Pdsleepcfg2
Sram If18 Apd - Pdsleepcfg2
Sram If19 Apd - Pdsleepcfg2
Sram If20 Apd - Pdsleepcfg2
Sram If21 Apd - Pdsleepcfg2
Sram If22 Apd - Pdsleepcfg2
Sram If23 Apd - Pdsleepcfg2
Sram If24 Apd - Pdsleepcfg2
Sram If25 Apd - Pdsleepcfg2
Sram If26 Apd - Pdsleepcfg2
Sram If27 Apd - Pdsleepcfg2
Sram If28 Apd - Pdsleepcfg2
Sram If29 Apd - Pdsleepcfg3
Sram If0Ppd - Pdsleepcfg3
Sram If1Ppd - Pdsleepcfg3
Sram If2Ppd - Pdsleepcfg3
Sram If3Ppd - Pdsleepcfg3
Sram If4Ppd - Pdsleepcfg3
Sram If5Ppd - Pdsleepcfg3
Sram If6Ppd - Pdsleepcfg3
Sram If7Ppd - Pdsleepcfg3
Sram If8Ppd - Pdsleepcfg3
Sram If9Ppd - Pdsleepcfg3
Sram If10 Ppd - Pdsleepcfg3
Sram If11 Ppd - Pdsleepcfg3
Sram If12 Ppd - Pdsleepcfg3
Sram If13 Ppd - Pdsleepcfg3
Sram If14 Ppd - Pdsleepcfg3
Sram If15 Ppd - Pdsleepcfg3
Sram If16 Ppd - Pdsleepcfg3
Sram If17 Ppd - Pdsleepcfg3
Sram If18 Ppd - Pdsleepcfg3
Sram If19 Ppd - Pdsleepcfg3
Sram If20 Ppd - Pdsleepcfg3
Sram If21 Ppd - Pdsleepcfg3
Sram If22 Ppd - Pdsleepcfg3
Sram If23 Ppd - Pdsleepcfg3
Sram If24 Ppd - Pdsleepcfg3
Sram If25 Ppd - Pdsleepcfg3
Sram If26 Ppd - Pdsleepcfg3
Sram If27 Ppd - Pdsleepcfg3
Sram If28 Ppd - Pdsleepcfg3
Sram If29 Ppd - Pmc
- PolDev
Clk - PolHost
Clk - Rbbkeepst
- Sdio0
- Sdio1
- SramIf0
- SramIf1
- SramIf2
- SramIf3
- SramIf4
- SramIf5
- SramIf6
- SramIf7
- SramIf8
- SramIf9
- Sram
If10 - Sram
If11 - Sram
If12 - Sram
If13 - Sram
If14 - Sram
If15 - Sram
If16 - Sram
If17 - Sram
If19 - Sram
If20 - Sram
If21 - Sram
If22 - Sram
If23 - Sram
If24 - Sram
If25 - Sram
If26 - Sram
If27 - Sram
If28 - Sram
If29 - Starten0
ClrAcmp - Starten0
ClrAdc0 - Starten0
ClrCt32bit0 - Starten0
ClrCt32bit1 - Starten0
ClrCt32bit3 - Starten0
ClrDmac0 - Starten0
ClrDmic0 - Starten0
ClrFlexcomm0 - Starten0
ClrFlexcomm1 - Starten0
ClrFlexcomm2 - Starten0
ClrFlexcomm3 - Starten0
ClrFlexcomm4 - Starten0
ClrFlexcomm5 - Starten0
ClrFlexcomm14 - Starten0
ClrFlexcomm15 - Starten0
ClrGpio Int0 Irq0 - Starten0
ClrGpio Int0 Irq1 - Starten0
ClrGpio Int0 Irq2 - Starten0
ClrGpio Int0 Irq3 - Starten0
ClrHwvad0 - Starten0
ClrHypervisor - Starten0
ClrMrt0 - Starten0
ClrNshsgpio Int0 - Starten0
ClrNshsgpio Int1 - Starten0
ClrRng - Starten0
ClrSct0 - Starten0
ClrSecureviolation - Starten0
ClrUtick0 - Starten0
ClrWdt0 - Starten0
SetAcmp - Starten0
SetAdc0 - Starten0
SetCt32bit0 - Starten0
SetCt32bit1 - Starten0
SetCt32bit3 - Starten0
SetDmac0 - Starten0
SetDmic0 - Starten0
SetFlexcomm0 - Starten0
SetFlexcomm1 - Starten0
SetFlexcomm2 - Starten0
SetFlexcomm3 - Starten0
SetFlexcomm4 - Starten0
SetFlexcomm5 - Starten0
SetFlexcomm14 - Starten0
SetFlexcomm15 - Starten0
SetGpio Int0 Irq0 - Starten0
SetGpio Int0 Irq1 - Starten0
SetGpio Int0 Irq2 - Starten0
SetGpio Int0 Irq3 - Starten0
SetHwvad0 - Starten0
SetHypervisor - Starten0
SetMrt0 - Starten0
SetNshsgpio Int0 - Starten0
SetNshsgpio Int1 - Starten0
SetRng - Starten0
SetSct0 - Starten0
SetSecureviolation - Starten0
SetUtick0 - Starten0
SetWdt0 - Starten1
ClrCasper - Starten1
ClrCt32bit2 - Starten1
ClrCt32bit4 - Starten1
ClrDmac1 - Starten1
ClrFlexcomm6 - Starten1
ClrFlexcomm7 - Starten1
ClrFlexspi - Starten1
ClrGpio Int0 Irq4 - Starten1
ClrGpio Int0 Irq5 - Starten1
ClrGpio Int0 Irq6 - Starten1
ClrGpio Int0 Irq7 - Starten1
ClrI3c0 - Starten1
ClrMu - Starten1
ClrOs Event Timer Wu - Starten1
ClrPmic - Starten1
ClrPowerquad - Starten1
ClrPuf - Starten1
ClrRtc Lite0 Alarm OrWakeup - Starten1
ClrSdio0 - Starten1
ClrSdio1 - Starten1
ClrSha - Starten1
ClrShsgpio Int0 - Starten1
ClrShsgpio Int1 - Starten1
ClrUsb Irq - Starten1
ClrUsb Needclk - Starten1
SetCasper - Starten1
SetCt32bit2 - Starten1
SetCt32bit4 - Starten1
SetDmac1 - Starten1
SetFlexcomm6 - Starten1
SetFlexcomm7 - Starten1
SetFlexspi - Starten1
SetGpio Int0 Irq4 - Starten1
SetGpio Int0 Irq5 - Starten1
SetGpio Int0 Irq6 - Starten1
SetGpio Int0 Irq7 - Starten1
SetI3c0 - Starten1
SetMu - Starten1
SetOs Event Timer Wu - Starten1
SetPmic - Starten1
SetPowerquad - Starten1
SetPuf - Starten1
SetRtc Lite0 Alarm OrWakeup - Starten1
SetSdio0 - Starten1
SetSdio1 - Starten1
SetSha - Starten1
SetShsgpio Int0 - Starten1
SetShsgpio Int1 - Starten1
SetUsb Irq - Starten1
SetUsb Needclk - Usbhsphy