Struct rp_pac::dma::Channel

pub struct Channel { /* private fields */ }

Implementations

impl Channel

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn read_addr(self) -> Reg<u32, RW>

DMA Channel 5 Read Address pointer

pub const fn write_addr(self) -> Reg<u32, RW>

DMA Channel 5 Write Address pointer

pub const fn trans_count(self) -> Reg<u32, RW>

DMA Channel 5 Transfer Count

pub const fn ctrl_trig(self) -> Reg<CtrlTrig, RW>

DMA Channel 5 Control and Status

pub const fn al1_ctrl(self) -> Reg<u32, RW>

Alias for channel 5 CTRL register

pub const fn al1_read_addr(self) -> Reg<u32, RW>

Alias for channel 5 READ_ADDR register

pub const fn al1_write_addr(self) -> Reg<u32, RW>

Alias for channel 5 WRITE_ADDR register

pub const fn al1_trans_count_trig(self) -> Reg<u32, RW>

Alias for channel 5 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.

pub const fn al2_ctrl(self) -> Reg<u32, RW>

Alias for channel 5 CTRL register

pub const fn al2_trans_count(self) -> Reg<u32, RW>

Alias for channel 5 TRANS_COUNT register

pub const fn al2_read_addr(self) -> Reg<u32, RW>

Alias for channel 5 READ_ADDR register

pub const fn al2_write_addr_trig(self) -> Reg<u32, RW>

Alias for channel 5 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.

pub const fn al3_ctrl(self) -> Reg<u32, RW>

Alias for channel 5 CTRL register

pub const fn al3_write_addr(self) -> Reg<u32, RW>

Alias for channel 5 WRITE_ADDR register

pub const fn al3_trans_count(self) -> Reg<u32, RW>

Alias for channel 5 TRANS_COUNT register

pub const fn al3_read_addr_trig(self) -> Reg<u32, RW>

Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.

pub const fn dbg_ctdreq(self) -> Reg<DbgCtdreq, RW>

Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

pub const fn dbg_tcr(self) -> Reg<u32, RW>

Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

Trait Implementations

impl Clone for Channel

fn clone(&self) -> Channel

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Channel

fn eq(&self, other: &Channel) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Channel

impl Eq for Channel

impl Send for Channel

impl StructuralPartialEq for Channel

impl Sync for Channel