#[repr(transparent)]pub struct IcFsSclLcnt(pub u32);
Expand description
Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
Tuple Fields§
§0: u32
Implementations§
Source§impl IcFsSclLcnt
impl IcFsSclLcnt
Sourcepub const fn ic_fs_scl_lcnt(&self) -> u16
pub const fn ic_fs_scl_lcnt(&self) -> u16
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to ‘IC_CLK Frequency Configuration’. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.
Sourcepub fn set_ic_fs_scl_lcnt(&mut self, val: u16)
pub fn set_ic_fs_scl_lcnt(&mut self, val: u16)
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to ‘IC_CLK Frequency Configuration’. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.
Trait Implementations§
Source§impl Clone for IcFsSclLcnt
impl Clone for IcFsSclLcnt
Source§fn clone(&self) -> IcFsSclLcnt
fn clone(&self) -> IcFsSclLcnt
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read more