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Module rp_pac::pio::regs

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Structs§

  • PIO control register
  • The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here.
  • FIFO debug register
  • FIFO levels
  • FIFO status register
  • Write-only access to instruction memory location 30
  • Interrupt status after masking & forcing for irq0
  • State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines – any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts – see e.g. IRQ0_INTE.
  • Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.
  • Current instruction address of state machine 3
  • Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
  • Execution/behavioural settings for state machine 0
  • Read to see the instruction currently addressed by state machine 3’s program counter Write to execute an instruction immediately (including jumps) and then resume execution.
  • State machine pin control
  • Control behaviour of the input/output shift registers for state machine 0