Struct rp_pac::otp::Otp

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pub struct Otp { /* private fields */ }

Expand description

SNPS OTP control IF (SBPI and RPi wrapper control)

Implementations§

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pub const fn sw_lock(self, n: usize) -> Reg<SwLock, RW>

Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page.

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pub const fn sbpi_instr(self) -> Reg<SbpiInstr, RW>

Dispatch instructions to the SBPI interface, used for programming the OTP fuses.

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pub const fn sbpi_wdata(self, n: usize) -> Reg<u32, RW>

SBPI write payload bytes 3..0

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pub const fn sbpi_rdata(self, n: usize) -> Reg<u32, RW>

Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0.

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pub const fn sbpi_status(self) -> Reg<SbpiStatus, RW>

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pub const fn usr(self) -> Reg<Usr, RW>

Controls for APB data read interface (USER interface)

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pub const fn dbg(self) -> Reg<Dbg, RW>

Debug for OTP power-on state machine

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pub const fn bist(self) -> Reg<Bist, RW>

During BIST, count address locations that have at least one leaky bit

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pub const fn crt_key(self, n: usize) -> Reg<u32, RW>

Word 0 (bits 31..0) of the key. Write only, read returns 0x0

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pub const fn critical(self) -> Reg<Critical, RW>

Quickly check values of critical flags read during boot up

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pub const fn key_valid(self) -> Reg<KeyValid, RW>

Which keys were valid (enrolled) at boot time

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pub const fn debugen(self) -> Reg<Debugen, RW>

Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key’s value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key’s value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags.

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pub const fn debugen_lock(self) -> Reg<DebugenLock, RW>

Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset.

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pub const fn archsel(self) -> Reg<Archsel, RW>

Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module.

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pub const fn archsel_status(self) -> Reg<ArchselStatus, RW>

Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update.

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pub const fn bootdis(self) -> Reg<Bootdis, RW>

Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register.

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