Struct rp_pac::pio::Pio

Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

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pub const fn rxf(self, n: usize) -> Reg<u32, RW>

Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

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pub const fn irq(self) -> Reg<Irq, RW>

State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines – any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts – see e.g. IRQ0_INTE.

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pub const fn irq_force(self) -> Reg<IrqForce, RW>

Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.

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pub const fn input_sync_bypass(self) -> Reg<u32, RW>

There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes.

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pub const fn dbg_padout(self) -> Reg<u32, RW>

Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

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pub const fn dbg_padoe(self) -> Reg<u32, RW>

Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

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pub const fn dbg_cfginfo(self) -> Reg<DbgCfginfo, RW>

The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here.

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pub const fn instr_mem(self, n: usize) -> Reg<InstrMem, RW>

Write-only access to instruction memory location 0

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pub const fn sm(self, n: usize) -> StateMachine

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pub const fn rxf_putget(self, n: usize) -> RxfPutGet

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pub const fn gpiobase(self) -> Reg<Gpiobase, RW>

Relocate GPIO 0 (from PIO’s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable).

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