Struct Pll

pub struct Pll { /* private fields */ }

Implementations

impl Pll

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn cs(self) -> Reg<Cs, RW>

Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz

pub const fn pwr(self) -> Reg<Pwr, RW>

Controls the PLL power modes.

pub const fn fbdiv_int(self) -> Reg<FbdivInt, RW>

Feedback divisor (note: this PLL does not support fractional division)

pub const fn prim(self) -> Reg<Prim, RW>

Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2

pub const fn intr(self) -> Reg<Intr, RW>

Raw Interrupts

pub const fn inte(self) -> Reg<Inte, RW>

Interrupt Enable

pub const fn intf(self) -> Reg<Intf, RW>

Interrupt Force

pub const fn ints(self) -> Reg<Ints, RW>

Interrupt status after masking & forcing

Trait Implementations

impl Clone for Pll

fn clone(&self) -> Pll

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Pll

fn eq(&self, other: &Pll) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Pll

impl Eq for Pll

impl Send for Pll

impl StructuralPartialEq for Pll

impl Sync for Pll