Struct rp_pac::powman::regs::Vreg

#[repr(transparent)]
pub struct Vreg(pub u32);

Voltage Regulator Settings

Tuple Fields

0: u32

Implementations

impl Vreg

pub const fn hiz(&self) -> bool

high impedance mode select 0=not in high impedance mode, 1=in high impedance mode

pub fn set_hiz(&mut self, val: bool)

high impedance mode select 0=not in high impedance mode, 1=in high impedance mode

pub const fn vsel(&self) -> u8

output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V

pub fn set_vsel(&mut self, val: u8)

output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V

pub const fn update_in_progress(&self) -> bool

regulator state is being updated writes to the vreg register will be ignored when this field is set

pub fn set_update_in_progress(&mut self, val: bool)

regulator state is being updated writes to the vreg register will be ignored when this field is set

Trait Implementations

impl Clone for Vreg

fn clone(&self) -> Vreg

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Vreg

fn default() -> Vreg

Returns the “default value” for a type.

impl PartialEq for Vreg

fn eq(&self, other: &Vreg) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Vreg

impl Eq for Vreg

impl StructuralPartialEq for Vreg