Struct rp_pac::powman::regs::VregLpEntry
source · #[repr(transparent)]pub struct VregLpEntry(pub u32);
Expand description
Voltage Regulator Low Power Entry Settings
Tuple Fields§
§0: u32
Implementations§
source§impl VregLpEntry
impl VregLpEntry
sourcepub const fn hiz(&self) -> bool
pub const fn hiz(&self) -> bool
high impedance mode select 0=not in high impedance mode, 1=in high impedance mode
sourcepub fn set_hiz(&mut self, val: bool)
pub fn set_hiz(&mut self, val: bool)
high impedance mode select 0=not in high impedance mode, 1=in high impedance mode
sourcepub const fn mode(&self) -> bool
pub const fn mode(&self) -> bool
selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)
sourcepub fn set_mode(&mut self, val: bool)
pub fn set_mode(&mut self, val: bool)
selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)
sourcepub const fn vsel(&self) -> u8
pub const fn vsel(&self) -> u8
output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V
sourcepub fn set_vsel(&mut self, val: u8)
pub fn set_vsel(&mut self, val: u8)
output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V
Trait Implementations§
source§impl Clone for VregLpEntry
impl Clone for VregLpEntry
source§fn clone(&self) -> VregLpEntry
fn clone(&self) -> VregLpEntry
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read moresource§impl Default for VregLpEntry
impl Default for VregLpEntry
source§fn default() -> VregLpEntry
fn default() -> VregLpEntry
source§impl PartialEq for VregLpEntry
impl PartialEq for VregLpEntry
impl Copy for VregLpEntry
impl Eq for VregLpEntry
impl StructuralPartialEq for VregLpEntry
Auto Trait Implementations§
impl Freeze for VregLpEntry
impl RefUnwindSafe for VregLpEntry
impl Send for VregLpEntry
impl Sync for VregLpEntry
impl Unpin for VregLpEntry
impl UnwindSafe for VregLpEntry
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)